Because I have used Vivado before, I thought the HW training will go easier and quicker than SW training for Vitis, which was the first time I have used it (more than trying to see what it is all about and what it has in addition to the Xilinx SDK). It looks like I was wrong and I am not sure what was the problem: the fact that I was using Vivado for Linux in a VM machine running on Windows 10 or because it was a new version (2021.2). I have worked before with 2018.2 and 2019.1 and 2 editions installed on Windows 10.
Vivado hanging
Problems started at Lab 2 of the HW training when I get stuck after I give the command to generate the design wrapper.
I get an error message related to sigasi-cache which could not be found and that Vivado became unstable. I tried to finish the wrapper creation but Vivado didn’t respond anymore.
I finally restart the VM machine, restart Vivado but the message came again.
Of course, I started to search for a solution on the Internet but none was solving my problem.
I was suggested to change the syntax checker from sigasi to Vivado, and when trying, I got another error message saying that a shortcut file can not be found, so the change had no effect.
I deleted the file of the current project (Lab2) and tried to start again the steps, thinking that maybe I missed something along the path—the same result.
I also must say that sometimes, all get stuck, not only Vivado, so I had to restart the Linux VM machine.
Trying to kill the wrapper creation process, I found (from forums) that in Vivado a task can be killed only by closing Vivado.
In another forum answer was suggested to change the sigasi-cache location, therefore I looked in the folder indicated in the post to see where in the default location is this folder (/home/training/.Xilinx/Vivado/2021.2/). There was no sigasi-cache and what attract my attention was that the Vivado folder (in /home/training/.Xilinx) displayed a lock in the folder icon. I verified ownership of the folder and I found it belonged to the root (compared to, for example, Vitis, whose owner was training user).
I changed the ownership of /home/training/.Xilinx/Vivado/2021.2/ and I restarted the process and it seemed to work. Looking in the up mentioned folder, I saw that the sigasi-cache appeared together with other files created by Vivado.
I moved forward in the training but then I get again new hangs of Vivado when in Lab4 we were introduced to the use of TCL. Trying to add a new port to the block design using create_bd_port tcl command, resulted in another hanging of Vivado. I started again and finally, I decided to change the text editor syntax analyzer from sigasi to vivado. This seemed to solve the problem.
Updating hardware specification
Another problem I encounter was related to the updating of hardware specifications. This is a problem with Vitis and not with Vivado.
During the training labs, we had to make modifications to the hardware specification (change in the customization of Zynq UltraScale IP, adding PL blocks (BRAM), therefore, the new hardware platform had to be exported to Vitis.
The need of reexporting the hardware platform occurred also as I forgot to make some customization and, when testing the software with the platform I saw it was not working. So, I went back to Vivado and corrected the configurations or added the necessary configurations. When exporting, I selected to overwrite the old hardware file existing in the Vitis folder where the hardware platform was exported the first time.
In both cases I noticed that issuing the following sequence of commands didn’t produce a working system: Update Hardware specification, Build (platform selected), New Application Project, Run.
I also used Clean Project command before Bild (the platform) to be sure the platform was built from a clean space. Did I forget something?
When I deleted the platform and re-created it with New Platform Project wizard, selected the new .xsa file, build it, and then re-created also the Application project, the system worked.
Other problems
Some other problems occurred, some that were due to missing some configuration of the Zynq Ultrascale IP or because the hardware configuration was not updated when needed.
Missing the configuration of DDR4 memory resulted in the impossibility to start the application. The error Exit point of FSBL is not hit was issued because the DDR4 memory could not be read (reading/writing cycles constraints not met).
After including a BRAM block in the hardware platform I have updated the hardware platform in Vitis and created the application for testing reading speeds between BRAM memory locations and between DDR4 memory with or without DMA. Running the application, the selection of the number of bytes to transfer was displayed
Enter number of words you want to transfer:
1=256; 2=512; 3=1024; 4=2048;
I selected option 1 and then the menu to choose the type of transfer was displayed.
Enter 1 for BRAM to BRAM transfer
Enter 2 for BRAM to DDR4 transfer
Enter 3 for DDR4 to DDR4 transfer
Enter 4 to exit
I entered option 1, BRAM to BRAM transfer, and the system hung. There was no way to stop the application so I had to stop Vitis.
Starting again VITIS and running again the application, I selected option 3 for transfer type (DDR4 to DDR4), and the application ran without problems. This make me think that there was a problem with inserting BRAM controller and BRAM memory when creating the hardware platform.
I went back to Vivado, verified all steps of creating the BRAM memory, and saw it was all as indicated in the Lab. The conclusion was that in Vitis, the new platform was not updated so, I deleted the old HW platform and recreated it and the application. This time the application was running as expected for all numbers of words selected and for all transfer types.
Documenting the work
This blog should have included screenshots of the problems encountered during the HW training: Vivado hung, Bitstream generated message displayed but Vivado still waiting for the task to return, the application blocked when trying to read BRAM memory, and Vitis was unresponsive or unable to exit from running the application etc. Unfortunately, I didn’t take those screenshots. Being behind schedule with the training and blog creation, my main objective was to find the solution to the problem that was blocking me as soon as possible in order to make an advance and hoping to recreate the problem and document it later. I think I don’t have time now to do this so, I will only provide a list of searches I made in my attempt to solve different problems that I hope will be of help to others if they will face the same obstacles. The list is compiled from the browser History, with many other searches being omitted as they were related to more general topics such as Installing Xilinx tools - at a moment I was thinking to reinstall Vivado and Vitis to solve the permission problem, the Linux commands and their options, and so on.
Searches
Vivado hanging (trying to find out why Vivado hangs when trying to generate wrapper code)
Vivado hangs a lot while waiting for child processes /support.xilinx.com
vivado 2021.2 freezing point - Google Search /www.google.com
Vivado GUI hangs while opening Block Design / support.xilinx.com
Why does the IDE halt (freeze) when opening the top level design file the first time it is used? /
support.xilinx.com
Why does Vivado 2021.2 get stuck installing when it reaches the "Final Processing..." step? /
support.xilinx.com
Xilinx/Vivado/2021.2/shortcuts/shortcuts.xml (No such file or directory) - Google Search /www.google.com
I installed the Vivado Design Suite 2021.2 software, but I can't find a way to invoke the software. There is no desktop icon, nothing in the startup menu, and no executables in the Vivado folder. /support.xilinx.com
Vivado 2021.1 installation produce no shortcut and program group, also a license question /
support.xilinx.com
[Vivado 12-106] *** Exception: java.io.FileNotFoundException: /home/training/.Xilinx/Vivado/2021.2/sigasi-cache/.cache (No such file or directory) (See /home/training/vivado_pid4506.debug) - Google Search /www.google.com
Everytime I open Vivado 2021.2, it crashes and shows detailes below. Can somebody help solve this problem? /support.xilinx.com
Killing a task in Vivado (trying to find out how to stop/exit Vivado tasks without exiting Vivado)
Can I kill a background task? /support.xilinx.com
kill a task in vivado - Google Search / www.google.com
Again searching for why Vivado hangs
.Xilinx/Vivado/2021.2/shortcuts/shortcuts.xml (No such file or directory) - Google Search /www.google.com
76539 - Vivado ML Edition 2021.x - Known Issues /support.xilinx.com
no vivado SDK shortcut !/ support.xilinx.com
Vivado hangs due to sigasi cache utilizing significant space /support.xilinx.com
Sigasi cache not found - Google Search /www.google.com
Sigasi cache - Google Search / www.google.com
Vivado 2021.2 is the .Xilinx/Vivado folder locked? - Google Search /www.google.com
Vivado 2021.2 is the .Xilinx/Vivado folder locked? - Google Search /www.google.com
Changing ownership (.Xilinx/Vivado folder was owned by root and not allowed to create sigasi-cache and other files)
change owner of .Xilinx/Vivado file - Google Search /www.google.com
How to change File permission / support.xilinx.com
Using the Zynq SoC Processing System — Embedded Design Tutorials 2021.2 documentation
/xilinx.github.io
Still hanging (after solving the permission access to files in .Xilinx/Vivado folder)
Vivado GUI hangs while opening Block Design /support.xilinx.com
Vivado 2021.2 customize ip hangs up - Google Search / www.google.com
Why vivado crashes when i try to Re-Customize IP? / support.xilinx.com
Missed a clock connection when customizing Zynq Ultrascale block (part of Lab 2)
[BD 41-758] The following clock pins are not connected to a valid clock source /support.xilinx.com
zynq_ultra_ps_e_0/maxihpm0_lpd_aclk - Google Search / www.google.com
Missed the configuration of DDR4 memory (part of Lab2) (the default configuration – DDR4 – was used instead of LPDDR4 needed for Micron memory available on Ultra96 board)
Exit point of FSBL is not hit - Google Search / www.google.com
Vitis error: Exit breakpoint of FSBL not hit / support.xilinx.com
Finding the BDF (Board Design File) for Ultra96 (thought maybe is simpler to start the project using a board design file. Searched on Avnet Github repository. There are BDFs also for other boards from Avnet)
bdf/ultra96v2 at master · Avnet/bdf · GitHub / github.com
bdf/ultra96v2/1.2 at master · Avnet/bdf · GitHub /github.com
Actions · Avnet/bdf · GitHub /github.com
GitHub - Avnet/bdf: Avnet Board Definition Files / github.com
zedboard.org/ zedboard.org
bdf/ultra96v2/1.1 at master · Avnet/bdf · GitHub /github.com
VIvado hanging again when creating new ports
Vivado hangs a lot while waiting for child processes /support.xilinx.com
Vivado 2021.2 create_bd_port command hangs Vivado - Google Search / www.google.com
create_bd_port command hangs Vivado - Google Search / www.google.com
Not reading BRAM memory
Microbalze Vitis bug：cannot suspend TCF error report Stalled on memory access_Bigbeea的博客-CSDN博客 / blog.csdn.net
cannot suspend tcf error report - Google Search / www.google.com