Need help with watchdog

Abhijit,

Watchdog is configured through a set of dedicated APIs in PSoC4. You can find more information on how to configure watchdog using these APIs from the PSoC Creator System Reference Guide, which is accessible from Help-> Documentation toolbar of Creator. I've attached a copy just in case.

Specifically, you can use the CySysWdtWriteCascade() API for your requirement.

Regards,

Arvind

Attachments:

system_reference_guide.pdf

Hi,

I am aware of the API. However I am not sure how the watchdog counters are arranged.

The problem here is that as the document PSoC_4_Architecture_TRM_001-85634_0B document does not mention the ordering and interrupt order of the three counters and their combinations in a block diagram way.

In my case, I wish to independently use the Counter 0 - Counter 1 for Reset purpose and Counter 2 for wake-up purpose.

That's where I needed clarity.

I have tried out the following configuration code but it does not work as expected.

In this code I had used Counter 1(Lower order)+Counter 0(Higher Order) for 5second and Counter 2 to generate wake-up every 2seconds.

#include <project.h>
#include <cyPm.h>
CY_ISR(Wakee)
{
    
   CySysWdtUnlock();
    CySysWdtResetCounters(CY_SYS_WDT_COUNTER0_RESET|CY_SYS_WDT_COUNTER1_RESET|CY_SYS_WDT_COUNTER2_RESET);
    CySysWdtClearInterrupt(CY_SYS_WDT_COUNTER0_INT);
    CySysWdtClearInterrupt(CY_SYS_WDT_COUNTER1_INT);
    CySysWdtClearInterrupt(CY_SYS_WDT_COUNTER2_INT);
    CySysWdtLock();
    CyIntClearPending(9);
}
int main()
{
    CyIntSetVector(9, Wakee);
    CyIntEnable(9);

    CySysWdtWriteMode(CY_SYS_WDT_COUNTER0,CY_SYS_WDT_MODE_INT_RESET);
    CySysWdtWriteMatch(CY_SYS_WDT_COUNTER0,0x7100); //5sec
    CySysWdtWriteClearOnMatch(CY_SYS_WDT_COUNTER0, 1u);
    CySysWdtWriteCascade(CY_SYS_WDT_CASCADE_01);
    CySysWdtWriteMode(CY_SYS_WDT_COUNTER1,CY_SYS_WDT_MODE_RESET);
    CySysWdtWriteMatch(CY_SYS_WDT_COUNTER1,0x0002); //5sec
    CySysWdtWriteClearOnMatch(CY_SYS_WDT_COUNTER1, 1u);
    CySysWdtWriteMatch(CY_SYS_WDT_COUNTER2,0x0FA00);   //2sec
    CySysWdtWriteMode(CY_SYS_WDT_COUNTER2,CY_SYS_WDT_MODE_INT);    
    CySysWdtWriteClearOnMatch(CY_SYS_WDT_COUNTER2, 1u);
    CySysWdtEnable(CY_SYS_WDT_COUNTER0_MASK|CY_SYS_WDT_COUNTER1_MASK|CY_SYS_WDT_COUNTER2_MASK);
    CySysWdtLock();

    CyGlobalIntEnable;

     while(1)
     {
          Pin_LED_Write(0);
          CyDelay(20);
          Pin_LED_Write(1);
          CySysPmDeepSleep();
     }
}

I have tried out several other combinations but nothing seams to work correctly.

Kindly help me on this.

Warm Regards,

Abhijit

You need the CySysWdtWriteMode() call. It configures the counters to either interrupt or reset mode.  CySysWdtWriteCascade() is used to cascade the counters together. Use  CySysWdtWriteToggleBit() to define the period for counter2 (can only be a power of 2).  CySysWdtWriteMatch(() is not supported for counter 2! Look at the function description in the System reference manual...

On the interrupt of counter 2, you need to reset counters 0 and 1. (Maybe also toggle a LED in the ISR, to see whether it gets called at all - you should try to get that working properly first...)

Hendrik,

Yes it is right CySysWdtWriteMatch(() is not supported for counter 2.

but can you roughly give an algo for cascading two timers to get >= 5 sec watchdog interrupt interval, Because I also want to cascade two timers to achieve >= 5 seconds of watchdog interrupt interval.

I agree with Abhijit that it is not described at any of document that in which sequence we use watchdog API to cascade two timers.

Can we achieve this by using counter 2 (As counter 2 has a 32-bit period)?