July 14th
More on the Solution to the Odd problem
The solution is working very well and hasn't failed yet.
My polled SPI drivers do not use the UCBUSY status bit at all.
All I do is poll the UCTXIFG flag on UCA1IFG prior a transmit and poll the UCRXIFG (also on UCA1IFG) flag after it.
When the UXRXIFG flag is set, the UCA1RXBUF is read irrespective of whether the value is used later or not.
Here's an example.
unsigned char sendchar1SPI(unsigned char d, unsigned char cntl_nCS) {
unsigned char b;
// Assert Chip Select if it was requested
if (cntl_nCS != 0) {
UCA1CTLW0 |= UCSWRST; // Ensure clean start
UCA1CTLW0 &= ~UCSWRST;
nCS_POUT &= ~DEVICE_nCS;
}
// Perform SPI transaction
while((UCA1IFG & UCTXIFG) == 0); // Ensure transmit buffer ready
UCA1TXBUF = d; // Transmit character
while((UCA1IFG & UCRXIFG) == 0); // Ensure transmission has completed
b = UCA1RXBUF;
// Negate Chip Select if it was requested
if (cntl_nCS != 0)
nCS_POUT |= DEVICE_nCS;
return b;
}
My MSO has confirmed this produces textbook timing.