W65C02S Address selection

Talk about your RAM chips.

The 6502 forums at http://forums.6502.org would be a better place to ask this question. The folks there will probably direct you to Garth Wilson's 6502 Primer webpage to learn about designing a 6502 computer: 6502 Primer index

The short answer is: you generate the chip select and write enable lines from the address bus and the clock. The 6502 Primer pages will give you way more information.

===Jac

I still have my 6502 powered Commodore PET computer.

The 6502 was an interesting chip, but unless you are really into nostalgia, there are just too many other modern chips that you could program to emulate the old 6502 software.

Still, if you are diligent enough, you can rebuild the 6502 devices.

Good luck.

DAB

Since the RAMs of today probably are much bigger than 64K, you don't need 'address decoding,' you need 'paging.'

First of all: small SRAM chips (by todays standards) are still available. Most engineers who build their own 6502 system use a 62256 (32KB) but smaller chips can easily be found, too. Interestingly, 64K SRAM chips (such as the 62512) are surprisingly difficult to find, but 128K chips are easy again.

Second: Regardless of how big of a RAM chip you use in a 6502 system, you will still need address decoding, because every 6502 system needs ROM, RAM and I/O. The original Apple-1 used 8K RAM and 256 bytes (yes bytes) of ROM, but the PIA takes up 4 addresses starting at $D010. Even if you use a 64KB RAM chip, you still need an address decoder to turn the RAM chip off for address areas where the ROM or the PIA (or whatever other chips you want to put into your system) need to be, because only one chip can be active on the data bus.

===Jac

First of all, I don't need a lesson in basic microprocessor/microcontroller design from you, Jac.  I have been designing with these chips since they have been market-relevant. 

I/O decoding is called 'I/O decoding.'  In the case of the 6502 it is 'memory mapped I/O decoding.'  This is in contrast with something like a Z80 with its explicit I/O decoding.  If you have a 32K-word SRAM on a 64K bus, the only practical way to map that is to use the fifteen bits the chip needs for addressing and the sixteenth for decoding, probably active high.  It is so hard to be think practically about the deliberately impractical. . .

For your I/O decoding you can use a '688 for the high-order bits and a 74hc138 or 74hc154 for the low-order decode, or jellybean or transistor glue logic, or a small PROM.

The idea that a system with paged memory wouldn't need bus decoding is weirdly weird.  This represents a step up from the project itself, which is merely weird.

In code-space you should put a ZIF socket or sockets.  Here, you can swap between a battery-backed dual-port SRAM for development, perhaps exchanging for a PROM later on.

Remember that you can always insert queue memory to buffer your I/Os if you want a more elastic set-up.

It is common to have Xs in the I/O map to simplify the decoder.  In cheap systems I have fashioned giant nor/nand gates out of wire-or diodes and a mosfet and resistor or two.  Seems crude, but it works.  Requires legit signal diodes, not the universally-loved-in-some-quarters PS diodes.

Yes, the 6502 page buffers let you do some very interesting things with just single commands.

The chip was amazing for its time.

DAB