Hi folks, during my master's degree on computer science, i worked on the development of an architecture for checking digital circuits, based on FPGA focused on data centers, and high performance systems. But due to lack of support from the developers and the final cost of the FPGA using in this project, my project was a long time stopped. Based on this, I had the idea of proposing as project from element14 to remodel the way verification is performed using the Arduino MKR Vidor 4000 provided by the contest.
The initial idea of my project consist in the development of an architecture to be inserted with the design under debug during circuit synthesis, and using these system i can be able to collect the data of the systems with the purpose of detect possible failures in the hardware description. The architecture is composed by 4 main blocks, and many integration signals hehehe.
- Trigger Logic: Detect when a possible failure happened inside the circuit. its use is directly related to the process of data collection of the circuit under analysis and in the information process of which specific part of the circuit under analysis happened the fault
- Config Memory: Used to configure the other blocks, will be configurated receiving the data Over I/O which can be serial communication, jtag and etc.
- Internal buffer: this memory, is responsible for storing a subset of faults within the circuit being analyzed. Its use is directly related to the large data rate that is commonly generated in a circuit debugging and low communication for sending this data directly
- I/O:The communication bridge between the FPGA and the real world aims to send and receive data directly from the serial controller, or jtag to collect the data and configure the debug blocks
The first architecture proposal consisted of a system capable of collecting the information of several modules at the same time, exploring the high capacity that the FPGA circuit has in harboring large projects within its architecture. However, this process can not be done in FPGAs with little free area, which leads us to the second architectural proposal
The new idea is to use a MKR VIDOR 4000 FPGA cluster to divide the parts of the project under test so that it is possible to partition all the blocks that make up a module under analysis so that it is possible to reduce both the the final cost of the check, how many possible timing problems (Slack) and also allow regression tests on the hardware description
Initiating the process with Arduino MKR VIDOR 4000
After a few time installing libraries and testing the board i'm finally turn on the board 
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