Let us assume that I want to create a signal like this:
Where:
Signal Name | Duration in μs ± 150 ns |
|---|---|
| T0H | 0.4 |
| T1H | 0.8 |
| T0L | 0.85 |
| T1L | 0.45 |
| Treset | > 50 |
The usual way to generate arbitrary signals is called "Bit banging". It requires software to set the output in the "HIGH" and "LOW" state in the exact timing given by the protocol. The timing requirements for this signal look pretty strict that I do not believe that this would be possible or at least not very reliable. So I am looking for some hardware support.
After a lot of head ache and reading datasheets the idea of using the PWM came into my mind.
Bit Banging with PWM
Let's look at the signal again:
- it starts always with "HIGH" and ends with "LOW" (except for reset which is always "LOW")
- length of signal is 1.25 μs (reset again an exception)
- 0.05 μs resolution (0.05 is the greatest common divisor of 1.25, 0.4, 0.85 and 0.45)
Exact Solution
The signal can be generated with PWM of 1/0.05 μs = 20 MHz frequency. Therefore the "alphabet" above translates to:
| Symbol | Duty % |
|---|---|
| "0" | 32 |
| "1" | 64 |
The PWM frequency of 20 MHz is quite high, can the signal be done approximated with lower frequency?
Reasonable Approximation
The odd thing about the spec for this signal is that it is not symmetric, i. E. the high time for "0" is not equal to the low time for "1" as I had expected. Since the rising edge of the signal is every 1.25 μs this allows the receiver to synchronize. The sampling presumably takes place at exactly the half of the time which explains the asymmetry: It gives a safety margin for the timing or rather does not require steep edges.
The tolerance for the falling edge is quite high. I did not recognize it at first sight, but when I converted the whole timing into nano seconds (ns) It's pretty clear:
| Signal Name | Time of Falling Edge Nominal [ns] | Time of Falling Edge Minimal [ns] | Time of Falling Edge Maximal [ns] |
|---|---|---|---|
| T0H | 400 | 350 | 550 |
| T1H | 800 | 650 | 950 |
This allows a much more reasonable approach:
Divide the 125 ns in three sections ad vary the duty cycle between 1/3 and 2/3 or in decimal:
| Symbol | Duty % |
|---|---|
| "0" | 33 |
| "1" | 66 |
The frequency in this case is only 2.4 MHz. That's much better!
Reset
The reset symbol is an exception - it does not fit in the above timing. It can be generated by 40 periods with a duty cycle of 0%.
Since we are able to generate the signal there is only one question left: What is this for?
Usage of the Signal
Did you recognize / guess the signal? What do you think it is for? 
(solution in the next blog post)
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