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Beginner’s workshop using Xilinx tools to build a hardware platform, develop bare metal applications, and execute on Ultra96-V2 hardware

 

To participate download Vivado 2020.1 and download Lab 2 below.   Also ensure that you meet the minimum requirements. *  

 

This workshop will get you up and running quickly with Xilinx’ free version of Vivado and Vitis tools. The Avnet Ultra96-V2 Single Board Computer will be the hardware target for several designs that are created during this workshop series. Through the course of the workshop, you’ll create a hardware platform in Vivado, then export your hardware to the Vitis SDK for software development. We’ll explore built-in drivers and example code and how to implement them in your project. We’ll also make use of the 96Boards Expansion connectors to add Click Boards to the hardware.

 

Session 2:

 

This is the second session in a 4 part series.  This workshop combines 4 build-along workshops with a lab between each session.  Completing each lab will give you a chance to apply what you learned during the workshop, while preparing for the next session.This workshop is free and open to all but to participate you will need to own or purchase the following products:

 

 

Buy KitBuy Kit

 

 

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* Minimum Requirements:   100 GB of free space and 6 GB of RAM.

 

Attend and Learn to Earn a Certificate:

 

Following this presentation there will be a short quiz to test your knowledge.   Complete the quiz and watch the presentation either live or On Demand to earn a certificate.   If you attend and demonstrate what you have learned, your certificate will be emailed to you.

 

To Earn a Certificate:image

 

  • View at least 30 minutes of the presentation
  • Score a 100% on the quiz

 

 

Dates and Register for Free:

 

Workshop:Dates and Missions:

Session 1 – Setup with Xilinx Tools

 

What You'll Learn:

  • Learn about the Xilinx toolset, including features and function of Vivado and Vitis
  • Learn where to get them and how to install them

Wednesday, 4th of August 2021

 

 

Lab 1:

  • Install the tools onto either a Windows or Linux Host PC

Session 2 – The Hardware Platform

 

What You'll Learn:

  • Learn what the hardware platform is and why you have to develop one
  • Compare this with a traditional flow like Raspberry Pi
  • Create a hardware platform for the Ultra96-V2 using presets
  • Add IP to the Programmable Logic

Wednesday, 11th of August 2021

 

  • Register Above for Free!

 

Lab 2:

  • In between Workshops #2 and #3, explore what you have created. This will help you as you begin working in Vitis, so you recognize what Vitis is pulling in to create software applications during Workshop #3.

Session 3 - Hello World on a Cortex-A53 and R5 Processor

 

What You'll Learn:

 

  • Learn about software platforms, BSP, example applications, build-in drivers, and hidden examples
  • Create all the necessary components to run Hello World on both an A53 and R5 processor
  • Connect your hardware and see the magic

Wednesday 18th of August 2021

 

 

Lab 3:

 

  • Develop and Run Memory and Peripheral Test Applications

Session 4 - Using Click Mezzanine and Click Boards

 

What You'll Learn:

 

  • Learn about the 96Boards expansion connector
  • See examples like the Click and ON Semi Dual Camera Mezzanines
  • Develop an application using the Click Mezzanine and Click Boards
  • Connect and run the example on your hardware

Wednesday 25th of August 2021

 

 

Lab 3:

  • Try updating the design so you can swap the LCD and the USB-UART
  • Try reading the 6DoF sensor in one of the Click Sites
  • Buy a different Click and get it working

Presenter:

 

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Bryan Fletcher , Technical Marketing Director, Avnet
I've been a fan of programmable logic technology since early in my career at Hewlett-Packard and Evans & Sutherland. I work now in Avnet's Products & Emerging Technologies group, currently working on Ultra96-V2, after working on many development boards over the years and as a Field Applications Engineer.
Attachments:
Element14 Ultra96-V2 Workshop Lab 2 v1_1.pdf