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  • Author Author: Catwell
  • Date Created: 18 Jun 2012 7:24 PM Date Created
  • Views 563 views
  • Likes 1 like
  • Comments 2 comments
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Allow mistakes in CPUs to gain a processing boost

Catwell
Catwell
18 Jun 2012

image

The inexact processor, more-or-less gets the job done (via Rice University)

 

Correctness is the definition of computer function. It is what programmers strive to attain. So, it might come as a surprise that a new counterintuitive computer chip is taking advantage of making mistakes.

 

 

A huge team that includes researchers from Rice University, Singapore’s Nanyang Technological University, Switzerland’s Center for Electronics and Microtechnology and UC Berkeley have produced an “inexact” computer chip that improves power efficiency, processing time and resource efficiency by allowing occasional mistakes. These “inexact” chips, also known as PCMOS, probabilistic complementary metal-oxide semiconductor, are about 15 times more efficient in speed, power, and size than current technology.

 

 

A paper released by the team has been recognized as the “best paper” at this year’s ACM International Conference on Computer Frontiers in Cagliari, Italy. The “inexact” chip works by allowing hardware that performs simple functions like addition and subtraction to make some mistakes. By statistical management of the probability of errors and limiting those calculations that cause errors, these researchers found they could cut down power consumption dramatically.

 

 

A method for improving efficiency of the chip is a process called “pruning”, in which rarely used parts of the chip’s digital circuitry are deactivated. Applying “pruning” allows for chips that are twice as fast, use half the energy and are half the size of conventional chips. It was published, that chips with 0.25% deviation improved power efficiency by 3.5 times compared to current chips. An 8% deviation proved an efficiency 15 times greater. “Confined voltage scaling” is another idea that helps power efficiency by taking advantage of the faster processing speed.

 

image

(Left) Original frame (Middle) Using an error of 0.54% (Right) Error of 7.58%. The frame on the left is 15 times more efficient. (via Rice University)

 

Project co-investigator Christian Enz of the CSEM, expressed his enormous confidence for this new technology, “Particular types of applications can tolerate quite a bit of error. For example, the human eye has a built-in mechanism for error correction.” Using these PCMOS, researchers were able to produce images with 0.25% error, which were practically identical to their correct counterpart.

 

 

Now the team plans to apply these chips in everything from hearing aids, cameras and even low cost tablet computers called I-slates. In fact, Krishna Palem, Professor of Computing at Rise announced that 50,000 I-slates are due to be delivered to India’s Mahabubnagar District middle schools and high schools in the next three years.

 

image

I-Slate (via Rice University)

 

The high efficiency of this “inexact” technology will allow the I-slate to be powered by solar panels similar to the ones used in calculators. The first batch of I-slates and hearing aids containing PCMOS, or “inexact” chips are expected to surface in 2013. So much for avoiding mistakes this whole time.

 

Cabe

http://twitter.com/Cabe_e14

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  • Catwell
    Catwell over 13 years ago in reply to DAB

    I like the power saving angle of these processors. However, if that is the cost to have a "less than accurate" processor, I might have to pass.

     

    Imagine collecting sensor data with this system.

     

    Cabe

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  • DAB
    DAB over 13 years ago

    An interesting approach.

    If I understand it right, you have a dynamic self limiting RISC processor.  I could see how this approach could save power and increase execution speed, but I would be a little concerned about the potential lack of deterministic execution of the software.

     

    I could also see a use in combining the compiler with the processor to burn in a fuse structure to use only those elements of the processor that the software would need.  The compiler would identify the code and data requirements, which in turn could be optimized to customize the processor structure for maximum speed and power solutions.

     

    This approach would definately lead to more efficient systems and still keep the deterministic features.

    I have an inherent distrust of processors that change themselves during use.  Skynet is just waiting to go sentient!

     

    Just a thought,

    DAB

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