Cadence Design Systems has announced the delivery of a new low-power flow which will enable faster design of leading-edge, low-power semiconductors.
Using a single, comprehensive design platform, the power flow will be used by engineers targeting the 65-nanometer process at the Semiconductor Manufacturing International Corporation (SMIC).
Through implementation of low-power chips utilising the company's 65-nanometer libraries, validation of the flow has been established.
There are also low-power technologies employed in the design such as power gating and multi-supply/multi-voltage techniques, which can reduce leakage and dynamic power consumption.
Steve Carlson, vice-president of product marketing at Cadence, said: "Power efficiency is a key requirement for many new semiconductors, yet designers sometimes think it's too new and therefore too risky."
In other semiconductor news, Interil Corporation has just announced that it has formed a new alliance with the Georgia Institute of Technology, which could lead to the development of new research programmes and facilities on-campus.