HDL Design House announces VITAL HVT 25VF behavioral model
Belgrade, Serbia – September 15th, 2010 - HDL Design House has announced the VITAL HVT 25VF behavioral simulation model, fully compliant to Silicon Storage Technology SST 25VF064C, 64 Mbit SPI Serial Dual I/O Flash, described in S71392-03-000 12/09 Specification. The HVT 25VF is accessed through the SPI (Serial Peripheral Interface) bus compatible protocol. The SPI bus consists of four control lines; Chip Enable (CE#) is used to select the device and data is accessed through the Serial Data Input (SI), Serial Data Output (SO) and Serial Clock (SCK). The HVT 25VF supports both Mode 0 (0,0) and Mode 3 (1,1) of SPI bus operations. Memory organization of the HVT 25VF SuperFlash memory array is in uniform 4 KByte erasable sectors with 32 Kbyte overlay blocks and 64 KByte overlay erasable blocks.
HVT 25VF VITAL model Key Features:
VHDL '93, Verilog and VITAL'2000 compliant
Required VITAL'2000 library for correct compilation
Timing backannotation by means of an SDF files
Models are written at a behavioral level, do not reveal intellectual property, and are not synthesizable
The VITAL HVT 25VF behavioral model completely simulates the functionality of real component behavior at all component timing behavior. This implies complete functionality, timing on inputs and outputs, all desired relations between input signals (setup/hold , pulse with, etc.) and all delays between inputs and outputs. In case any timing constraints are not satisfied, the VITAL HVT 25VF behavioral model detects timing violation and reports it by using standard VITAL functions. The code is written in Verilog and the model is highly portable across a range of simulators.
Flash memory instructions are used to read, write (Erase and Program) and configure the HVT 25VF. The instruction bus cycles are 8 bits each for commands (opcode), data and addresses. The Write-Enable (WREN) instruction must be executed prior to any write instruction. All instructions are synchronized off a high to low transition of CE#. Inputs will be accepted on the rising edge of SCK starting with the most significant bit. CE# must be driven low before an instruction is entered and must be driven high after the last bit of the instruction has been shifted in (except for Read, Read-ID, and Read-Status-Register instructions). Any low to high transition on CE#, before receiving the last bit of an instruction bus cycle, will terminate the instruction in progress and return the device to the standby mode. Instruction commands (opcode), addresses, and data are all input from the most significant bit (MSB) first.
The VITAL HVT 25VF behavioral model can be used for board-level and/or system level verification. In test environment, the device under test (DUT) is connected to the VITAL HVT 25VF component.
The VITAL HVT 25VF behavioral model can be used along with HDL DH SPI flash memory controller IP core (HIP 3100). The HIP 3100 IP core is an advanced controller for SPI flash memories which off-loads host CPU from direct data transfer control of PPI flash memory. The host CPU can program SPI controller specifying the type of data transfer (SPI instruction, address, data, etc.) and SPI controller executes requested transfer. For more information about HDL DH SPI flash memory controller IP core (HIP 3100), please visit http://www.hdl-dh.com/prodbroch/HIP3100.01.04.2009.pdf.
VITAL behavioral models are products of close cooperation of HDL Design House (HDL DH) and Free Model Foundry (FMF) company. HDL DH and FMF have developed thousands of VITAL models. The VITAL model package consists of VHDL and Verilog source code, memory preload files (when appropriate), FTM and SDF files, test cases package file and documentation. The HVT MX25L model and other VITAL models are available for download free of charge from the FMF website (http://www.freemodelfoundry.com).
About HDL Design House:
HDL Design House delivers leading-edge digital and analog, design and verification services and products in numerous areas of SoC and complex FPGA designs. The company develops IP cores and provides complete design and verification services for complex SoC projects. The company also delivers component (VITAL) models for major SoC product developers. Dedicated to fulfilling each customer's unique requirement, HDL Design House has established a reputation as a reliable partner with high-quality products and services, flexible licensing models, competitive pricing and responsible technical support. The company enables customers to concentrate on system-level work and be confident that the various system components have been fully and reliably engineered and tested.
Founded in 2001, HDL Design House has 60 employees in two design centers – in Belgrade and Cuprija (Serbia). The company was awarded ISO 9001:2000 and ISO 27001:2005 certifications in December 2006 and has achieved certifications from Direct Assessment Services (DAS), thereby meeting United Kingdom Accreditation Service (UKAS) regulatory requirements. With ISO 27001:2005 certification, the highest certification standard for information security available, HDL Design House becomes the first company in Serbia to comply with this standard. In 2006 the company was awarded the SME Exporter of the Year by Serbia Investment and Export Promotion Agency (SIEPA).
Founded in 1995, Free Model Foundry is dedicated to promoting standard modeling practices within the electrical engineering community. In particular, we support the use of VHDL, Verilog, and SystemVerilog modeling languages.
One service provided by FMF is to help IC and IP vendors increase the rate of adoption of their products by providing accurate, uniform, functional models to expedite evaluation and selection by designers of electronic systems. Our staff of experienced modeling engineers has developed models simulating over 11,000 parts and takes pride in the ease of use and accuracy of results its products offer.
Free Model Foundry (FMF) believes in free, open source distribution of simulation and analysis models of electronic components. It promotes the development, distribution and sharing of functional simulation models (with timing) for board level components and open source behavioral models for proprietary IP.
HDL Design House Marketing Team
Contact person: Milena Jovanovic
phone: +381(0)11 303 98 25