Today, I decided to check the pattern generator and logic analyzer features of the Analog Discovery 3. I have used a Microchip development board from the Curiosity Nano series with AVR16EB32 MCU, as a device under test unit. The AVR16EB32 MCU has support for configurable custom logic, which I configured to a simple AND gate, which uses PC1 and PC2 pins as inputs, and a PC3 pin as output. At the input of this gate was provided a pattern generated by a pattern generator and the output was captured by a logic analyzer. Below there is a block diagram of the setup that was performed during this test.
Here is a connection setup to the Curiosity Nano board:
I have created a simple program in C that setup CCL in the proper mode of AND gate with the requested pins. Here is a listing of this code:
#define F_CPU 3333333UL
#include <avr/io.h>
#include <util/delay.h>
int main(void)
{
PORTC.DIR &= ~PIN1_bm; // PC1 - LUT1 IN[0]
PORTC.DIR &= ~PIN2_bm; // PC2 - LUT1 IN[1]
PORTC.DIR |= PIN3_bm; // PC3 - LUT1 output
CCL.LUT1CTRLB = CCL_INSEL1_IN1_gc; // IO pin LUTn-IN1 input source
CCL.LUT1CTRLC = CCL_INSEL2_IN2_gc; // IO pin LUTn-IN2 input source
CCL.TRUTH1 = 0x40; // Configure Truth Table
CCL.LUT1CTRLA = CCL_OUTEN_bm; // Enable LUT0 output on IO pin
CCL.LUT1CTRLA |= CCL_ENABLE_bm; // Enable LUTs
CCL.CTRLA = CCL_ENABLE_bm; // Enable CCL module
PORTF.DIR |= PIN5_bm; // LED 0
while (1) {
PORTF.OUTSET = PIN5_bm;
_delay_ms(500);
PORTF.OUTCLR = PIN5_bm;
_delay_ms(500);
}
}
I have performed a compilation of this source with avr-gcc in version 14.2.0 under the Linux system with the following commands:
avr-gcc -mmcu=avr16eb32 -Os -o main.elf main.c avr-objcopy -O ihex main.elf main.hex
As a utility to flash the on-chip memory of the MCU, I have used an avrdude in version 8.1. The uploading of the output hex file was done with the following command:
./avrdude_Linux_64bit/bin/avrdude -c pkobn_updi -P usb -p avr16eb32 -U flash:w:main.hex Reading 222 bytes for flash from input file main.hex Writing 222 bytes to flash Writing | ################################################## | 100% 0.20 s Reading | ################################################## | 100% 0.06 s 222 bytes of flash verified Avrdude done. Thank you.
In WaveForms, I have created a pattern that uses DIO 1 and DIO 0 pins. The DIO 0 was configured as a clock type with a frequency of 1 kHz, while DIO 0 as a pulse with low to high transition. The created pattern was run in infinite mode. Below is a screenshot of this configuration.
The logic analyzer was configured to capture the DIO 2, DIO 1 and DIO 0 pins. It was configured for single shot capture. Below there is screenshot:
As presented in the attached screenshot, the configured AND gate in AVR16EB32 MCU worked properly.
The pattern generator and logic analyzer available on Analog Discovery 3 gives a big flexibility in the case of quick testing of protocol or DUTs, which do not require a high speed of sampling.
