I learned a trick from w2aew: how to measure current if you don't have a current probe. He's using a N-channel JFET as example. I adapted it to a P-channel type - the J176. w2aew describes this in a video. He also published the notes. Follow and understand that first, because I will focus on translating this to a P-channel circuit.

Current mirror

This is a nice trick to measure the current in a component if you don't have a sensitive current probe.

It's not perfect, but works surprisingly good.

You do this by putting a transistor in series with the part of the circuit you want to know the current of.

You tie the basis of the transistor to the collector.

image: current mirror. NPNs used because we're sinking current in the blog's circuit, if you use conventional current flow.

This will cause that there's maximum the basis-emitter drop over collector-emitter (because basis and collector are connected) is also that "diode" drop.

This is the start of the working point of the circuit. You have to add the diode drop voltage to the "original" supply voltage. The transistor is conducting.

Then because of magic (because of physics actually), the collector current running trough a similar transistor -  that has base and emitter attached to the first one - is virtually the same as the current running trough the original one.

You can measure that current by putting a serial resistor in the collector line, and checking the voltage over that resistor.

The N-channel Drain Current Measurement Circuit

Almost all tutorials use N-channel devices. So does w2aew. Here is his circuit:

image source: w2aew notes. This is a neat design that lets you see the curve on an oscilloscope in X - Y mode. Try it.

The P-channel Version

I'm translating that into a P-channel one. I'm using LTspice so that I can simulate some situations later.

If, like me, your brain is used to think NPN, N-channel, possitive power supplies, you'll need to flex a little.

image: translated wa2aew design to P-channel FET, all components at the same place.

There are several conventions on how to draw negative-voltage diagrams.

The one used here (above), puts ground at the bottom, and the negative supply on top. I've done that here to stay close to w2aew's drawing. Philips typically used this style too in their audio schematics.

Most put the ground level on top, and the supply at the bottom of the schematic (like below). I often do that - in particular when I have a symmetric design with positive and negative supplies.

image: the same diagram, with base on top and the supply voltage at the bottom of the diagram. (done in ms-paint : ) )

For my brain, the first one is easier to understand when following the explanation in w2aew's video.

The second one is easier when I'm investigating the circuit, visualising conventional current flow.

What has changed.

• supplies are inverted.
• The JFET is now P-channel
• the two transistors in the mirror are NPNs.

The Simulated Results

w2aew's JFET has a higher Gate-Source Cut-Off Voltage than mine (J310, somewhere between -2 -> -6.5 V, while mine is a J176 with 1 -> 4 V cut-off).

Here is his drawing of the results as recorded on an oscilloscope:

Here are mine, simulated in LTspice:

The red line is the ID of the FET. The Blue line the current trough R20 (closely mirroring the FET current).

I've added the green triangle voltage that is the source voltage for good measure. This is with gate at 0.5V

I'l build this up with real components in a follow-up blog, and see if I can get this as a curve on the scope ...

The difficult part is the triangle. I don't have a generator that can generate negative waves and negative DC offset. Maybe with the help of an op-amp adder / inverter ...