Datasheet confusion, re: layout instructions

Hi Andrew,

I've not looked in detail yet, but here's an overlay in case it helps (this was with ViewMate, great software but not intuitive to use):

(the green is top layer, becomes yellowish when the bottom layer (red) is underneath it).

EDIT: Maybe this one is easier to view.. I deleted some of the messy silkscreen:

Andrew,

I did not completely analyze the PCB, but you are right, they did not follow their own instructions.  The ground in particular does not show a separation of the high and low current paths.  It also appears that they have set themselves up for some ground loops (the red layer (bottom?) is connected to ground on both sides of the high current path, at E2 and E5).  I have seen other cases like this where a vendor specifies best practices, but then does not follow their own advice when building a reference design.

Gene

Thanks Shabaz.  I resorted to printing on transparencies and holding them together!  But I think that highlights what I was saying.  There doesn't look like there are any vias linking the top plane to the bottom plane which I thought would happen??  I think they haven't followed their own advice because they're not that bothered with what is happening at Vout as it still demonstrates functionality (as does my board for that matter.)  I've posted below what I think it should be.

I'm glad you think so and it isn't just me.  This is what I think should be the case:

So there are separate ground traces for Signal and Power.  Essentially Cout -ve becomes the star ground reference for the two nets.  Apart from that, the layout on their PCB seems to follow their layout instructions: so if the LTC1624 ground pin was removed from that top 'Z' plane with another ground plane for Ith/Run, Vfb, GND it would match pretty well.  The parts are difficult to place given their relative sizes - t he LTC1624 is about is about 5mmx8mm so the Schottky, Mosfet, Cout, Cin are all significantly larger so 'close' becomes very relative.

Hi Andrew,

I took a look at a different chip I've used in the past, just to see what the recommended layout is like. Here R10 and R6 form the feedback resistor divider:

Perhaps that can give some ideas. Also it could be worth querying from LT directly, letting them know that their datasheet makes no sense. They are responsive (I asked them a while back concerning some other chip).

Hi Andrew,

This text might help, from "Fundamentals of Power Supply Design" which is a TI book that I won in a competition a while back.

It places the resistors away from the switching area, to keep them away from the MOSFET and diode, to reduce switching noise pickup on that resistor node.

It agrees with the style of layout in the TI design mentioned earlier, but disagrees with the style of topology drawn in the LT datasheet.

That is helpful, thanks - I was trying to work out how the chip got power as VDD is connected through a capacitor and resistor, C4 and R4!  Checking the datasheet for the TPS40200, I think you must have an older version as it looks different in the version I saw.

Anyway, it is useful and if you compare the layout with Figure 9 for the LTC1624, they are pretty comparable.  In this version, we can see that GND pin is connected at the same point as the feedback divider (and compensation loop) at Cout (or C2 in this figure.)  That makes me think even more that the evaluation board layout was not done with quality output in mind, just capability.  I guess without getting hold of one I'll never know, but I will contact LT and see if they can clarify, good suggestion.  The layout notes in the TI datasheet are way clearer as well.

Doing more research on DC-DC switchers has given me even more insights into how wrong my layout was in respect to ground.  Clearly I need to follow that high-current path all the way to the output terminals and consider the ground connections for the low current control components accordingly. 

Can I ask two further questions:  in the TI datasheet it says "Traces carrying large AC currents should NOT be connected through a ground plane. Instead, use PCB traces on the top layer to conduct the AC current and use the ground plane as a noise shield."  Does this mean that the high current traces, including Ground traces, should be on the top layer with a solid ground plane underneath to which nothing is connected, except where ground routing on the top layer is impossible and needs to be routed on ground plane layer?  Here I'm imagining a 4-layer board with high current traces on top layer, then shielding Ground Plane (routed/split away from sensitive components), then signal ground plane, then signal traces.  Both shielding and signal ground planes connected at, where, Cout -ve? Vin -ve?

Hi Andrew,

Looks like we were typing responses at the same time : )

Regarding shield, they're suggesting that since the top copper can be used for the traces that carry high switching currents, then a different layer can act as a shield to prevent that switching noise to affect other circuitry. To do that, it doesn't overly matter where that shield is connected (it would matter for RF).

Incidentally, here's a layout from a computer board, using TPS51315 (PDF doc) I like looking at PCBs just to see what the designers did : )

It has integrated MOSFETs so the layout isn't the same, but again they have got the feedback node quite far from the high current areas.

The power ground is definitely using another layer too, since the stitching can be seen on the left and the right side of the photo, but since this is a large motherboard it will have many layers, so shielding is still possible.

I think we were yes, and nearly again although you got in first! 

From your text extract, yes, I'd picked up from reading the TI stuff (and an excellent article from Micro-Rohm) that the feedback circuit must be kept away from the switching node - actually all sensitive circuits.  Clearly figure 9 for the LTC1624 has the divider smack bang next to the Schottky and Inductor - although it seems a little better in their evaluation board layout in that they are only close to the Schottky ground terminal.  It's interesting that a lot of the images I see relating to these switching converters having the compensation capacitor and resistor connected to the feedback pin.  The LTC1624 doesn't have this setup, instead connecting compensation to ground.

Pictures of actual production pcbs are very useful so thanks for posting that.  I've been looking at SMD mosfets to close up the gaps - I can get one with similar/slightly better specs than the one I've currently got (through hole - which is a pain as the pin configuration is GDS rather than DGS) except for power dissipation.  I shall run some temp tests on a variety of loads to see what the score is: my calculations say it should be ok and the LTC board uses a misfit with the same low power dissipation.

I'm going to go for a 4-layer PCB next as it seems a lot easier for only a small additional cost.  So I was thinking components, high-current traces and high-current ground returns on top layer, signal traces where I can keep them away from the high-current traces; power (shielding) ground on layer 2; signal ground on layer 3 and traces on bottom layer when needed for routing.  That should avoid adding traces on either of the ground planes and breaking them.  Route the power ground away from sensitive components - that will make it an unusual shape of course but 4 layers will allow me a lot more flexibility in layout than the 2 layer board I currently have.

It would seem that from the image above, and what you note, that actually I could avoid high-current ground traces on the top layer and just stitch these through to layer 2.  That would seem to be against the layout advice TI give (which I quoted above) and also Micro-Rohm:

Next, PGND is essentially laid out as a single line on the top layer (as on the left in Figure 8). However, as a result of component arrangement and the like, there are cases in which a single continuous line is not possible. In such cases, PGND may be broken up and connected on the rear surface or by an internal layer, using vias (as on the right in Figure 8). Due to the influence of resistance and inductance of the vias, there may be increased losses and the noise level may be worsened, and so actual device should be used for thorough verification.

I wonder if having 6 layers+, as per the motherboard, allows for that as it could, for example, have the top layer, power ground layer 2, shielding ground layer 3 (uninterrupted).  I'm also now wondering if the resistance/inductance of vias is offset by much more control over ground loops by having the high-current ground follow under the high-current traces although that would then lose the benefit of a shielding layer in a 4-layer board.

So much to get my head around!  I'm going to end up the site expert on dc-dc switchers at this rate

Andrew,

Can I ask two further questions:  in the TI datasheet it says "Traces carrying large AC currents should NOT be connected through a ground plane. Instead, use PCB traces on the top layer to conduct the AC current and use the ground plane as a noise shield."  Does this mean that the high current traces, including Ground traces, should be on the top layer with a solid ground plane underneath to which nothing is connected, except where ground routing on the top layer is impossible and needs to be routed on ground plane layer? Here I'm imagining a 4-layer board with high current traces on top layer, then shielding Ground Plane (routed/split away from sensitive components), then signal ground plane, then signal traces.

In the top image, the ground plane (both Kelvin Gnd and Power Gnd) are shown in a single trace.  In the lower image, the Ground and the Kelvin Ground are more of a starred arrangement, where the high currents are passed through the thick trace and the low currents through a separate (thinner) trace.  This is a simple start, but the situation gets much more complicated when the high and low currents are a part of the ground plane flooding, where the there is a lot of copper, but it begins to take on convoluted shapes and exists on multiple layers, inter-stitched.  Do the large paths need to be on the top layer?  Mostly yes, because that is where the components in the high current path are.  The most direct connection (trying not to use vias) is the preferred method of connection.  When thinking of a solid ground plane on another layer, again you need to be careful about the possibility of mixing high and low currents, so if you need to stitch connections, try and do it with traces and vias, not necessarily vias to a flooded plane.

Both shielding and signal ground planes connected at, where, Cout -ve? Vin -ve?

Tie them at a single point.  I usually tie traces at the input side (ve).  From the source side, I star out a low current path and a high current path, never allowing then to reconnect to each other.  If I am adding a ground plane (shielding), it is also connected to the ground at the 'star' point and again, never allowing it to reconnect to the other ground paths.

Gene