What sort of things would you discuss - Z80 has such poor performance compared with modern processors that surely no one would use one in a new project ?
I haven't kept up with modern processors but suspect they can't match the interrupt capabilities of the Z80, and interrupts can really make a design sing.
I haven't kept up with modern processors but suspect they can't match the interrupt capabilities of the Z80, and interrupts can really make a design sing.
IM0 (Interrupt Mode 0) is exactly the same as the 8080 where the interrupting device places a CPU instruction on the data bus during an Interrupt Acknowledge cycle. This instruction is usually a singly byte RST instruction but can be any instruction one wishes. Not often implemented by hobbyists due to the additional hardware involved.
IM1 (Interrupt Mode 1) is just a simple RST 0038. When and interrupt is asserted the CPU calls the routine at memory address 0038H.
IM2 (Interrupt Mode 2) is popular for hardware designs with Z80 peripherals such as the PIO or CTC are present. To get this working, the programmer must firstly set the CPU's I (Interrupt Register) as the Page number (i.e. the most significant byte) of where the nominated 16-bit Interrupt Service Routine addresses will be placed, secondly configure the supporting peripherals to generate the required interrupt vector (i.e. the least significant byte of the address) to fetch the ISR address, and of course execute IM2 and EI (Enable Interrupt) instructions.
Upon exit from an ISR it is usual to perform an EI, RETI combination. The Z80 is configured so that the EI instruction does not become effective until the completion of the following (usually a RETI or RET) instruction.
However nested prioritised interrupts can be supported with the insertion of EI, NOP instructions at the beginning of ISRs but appropriate management is required to ensure correct operation.
