Discrete Analogue to Digital converter

That sounds cool. Can you post a picture of it or a schematic or do you have a question about it?

I have a video up on youtube of this working, it is based on a ramp counter, constant current linear ramp with comparator. I used an STC89C52 running at 20Mhz in 6T mode, this is based on the old 8051 microcontroller. With 20x4 LCD

We need a schematic - it's like home work - you only get marks if we can see your workings out  

For an A++ grade - try making it logarithmic !

MK

We need a schematic - it's like home work - you only get marks if we can see your workings out  

For an A++ grade - try making it logarithmic !

MK

Why would I want to convert a linear voltage scale to logarithmic 

A long time ago when an 8 bit monolithic ADC was expensive and the best you could buy was 12 bit, I had to design an auto ranging audio frequency level meter for BT. We wanted to be able to cover 14dB in each range with a worst case accuracy of 0.1dB which needs at least 10 bit resolution if you use a linear ADC. But if you use  a logarithmic ADC you only need 140 divisions rather than 1024. A single slope log converter can be made by replacing the current source with a resistor. Two comparators rather than 1 enables you to auto-cal it on every conversion. But you needed a decent capacitor - think we used a 10nF polystyrene one.

But now you can buy an I2C interfaced 16 bit converter with two differential input ports, one with very low offset for under £1 (an INA230) so the art of single, dual and even multi-slope converters has had its day 

MK

Nice, mine is a linear dc voltage display with raw A to D count of 19716 counts at 9V input to give me mV resolution, gives me just over 14bit resolution, no software filtering and no software linearity correction, pure raw Analogue linearity.

Is it just for fun or do you need it for something ?

I've seen people do similar things when they need an unexpected ADC and only have IO pins available. But they don't get very good results with standard pins and the processor supply for reference.

MK

I was bored, 5 iterations 10 days

More like 2 Saturdays 2 Sunday's and few evenings after work, spread over 10 days

but it is awesome to make and understand how these work, hp/agilent/keysight etc started out with dual slope adc and now have things like multislope or way more complex algorithms to significantly improve accuracy, how repeatable is your design both in accuracy and stability?

you should be able to find old schematics and descriptions of the older HP bench meters if you want to understand more about auto cal etc.

Thanks for sharing the schematic.  I am assuming that while Ramp control is 0V the capacitor charges and when the comparator trips it is detected in software... so my question is... is the ADC value obtained by a counter that runs during the capacitor charge cycle?  Or am I completely misunderstanding your design?

thanks, this is loosely based on a 1954 ramp counter principle.

begin, relese clamp start linear ramp charge, start For loop count, in the loop poll to detect comparator if not detected count increments, when comparator change detected stop count, display count value - reset counter and clamp ramp. repeat process.

the more linear the ramp is, the more accurate the ADC becomes.

i'm chassing the 1mV dragon.