Is it just for fun or do you need it for something ?
I've seen people do similar things when they need an unexpected ADC and only have IO pins available. But they don't get very good results with standard pins and the processor supply for reference.
but it is awesome to make and understand how these work, hp/agilent/keysight etc started out with dual slope adc and now have things like multislope or way more complex algorithms to significantly improve accuracy, how repeatable is your design both in accuracy and stability?
you should be able to find old schematics and descriptions of the older HP bench meters if you want to understand more about auto cal etc.
Thanks for sharing the schematic. I am assuming that while Ramp control is 0V the capacitor charges and when the comparator trips it is detected in software... so my question is... is the ADC value obtained by a counter that runs during the capacitor charge cycle? Or am I completely misunderstanding your design?
thanks, this is loosely based on a 1954 ramp counter principle.
begin, relese clamp start linear ramp charge, start For loop count, in the loop poll to detect comparator if not detected count increments, when comparator change detected stop count, display count value - reset counter and clamp ramp. repeat process.
the more linear the ramp is, the more accurate the ADC becomes.
Thanks. I guess I was on the right track then. I think commercial ADCs generally have an error that exceeds 1mV... so there is no shame in chasing 3mV or 4mV dragon.
And I guess you are in good company. Your Ramp Generator circuit resembles this one:
