AD5065 Dual DAC AXI
Introduction
This article describes the implementation of the AD5065_Dual_DAC_AXI IP and the motivation behind it. The author of this text assumes that the reader is familiar with Xilinx’s Vivado, Zedboard[1], AXI lite slave IP design and integration, and the AMS101 evaluation card[2].
Motivation
This IP was created in order interface and control the AD5065 DAC device that can be found on the AMS101 evaluation module. It is possible to replace the whole IP with software implementation of the SPI functionality in case the Zynq PS or a Micoblaze is used, however, by creating a dedicated IP, the designer has the opportunity to control the evaluation card without the use of a processor. Moreover originally the evaluation board belongs to the AC701 Evaluation Board, which is powered by an Artix chip. Because the controlled device is a DAC (one-directional form of communication – only outputs data, but does not sample/receive) the AD5056 IP block can only write data to the DAC, but not read back, therefore the designer is assuming that the application will be aware of the DAC configuration at any given time (in needed).
Operation
The AMS101 card features an XADC compatible connector, which has 4 GPIO pins in this case are used for the SPI protocol, where:
XADC pin connector
XADC pin | Functionality |
Pin17, GPIO1 | SCLK |
Pin18, GPIO0 | LDAC |
Pin19, GPIO3 | SYNC |
Pin20, GPIO2 | DIN(MOSI) |
The SCLK is the SPI clock, LDAC is a signal that allows the newly programmed configuration to become active, when LDAC=’0’, SYNC acts as SPI slave enable and Din is the input for the data. In this IP the LDAC is permanently set to ‘0’, so the DAC configuration is enabled as soon as the programming operation is completed. The SPI functionality is quite simple – The SPI takes transmission composed of 32-bit packages, each beginning by pulling the SYNC signal low. In the same time the data is being sent by starting with the MSB. The SCLK is used to synchronize the SYNC and the DIN signal.
AD5065 SPI timing diagram
The 32-bit word that is sent to the SPI has the following structure:
Figure 3 SPI data structure
- Bits 31 to 28 are not unused.
- Bits 27 to 24 are used to store the command tha the user wants to execute.
- Bits 23 to 20 are used to select the DAC that the use wants to configure.
- Bits 19 to 4 are used to store the DAC value that the user want to write to the DAC.
- Bits 3 to 0 are not used.
AD5065 command and address bits definition
The operation of the IP is tightly related to the SPI functionality – it takes only one input, which is the word that must be sent over to the DAC. Once the new data is received, it is being sent to the DAC automatically. Because this IP fulfils only the basic operation of the AD5056 and user cannot:
- Cannot read the configuration back.
- Cannot schedule an update operation with to LDAC.
However, whoever is using this IP, is welcome to modify the IP as needed in order to satisfy one’s requirements. There is also a RTL version that can operate without AXI. Its interface consists of only one input register:
Implementation
The IP implements a very simple state machine that is used to serialize the received word and sent it in a SPI format. Once the data has been sent the SPI enters an Idle state, which is constantly monitoring the word input and once a new command is received the state machine sends the new data over the SPI. The functionality is illustrated on the diagram below:
AD5065 flow diagram
For more details, check the IP source code. The IP has two versions – one with a native input (std_logic_vector) and one with AXI interface. The IP are identical in terms of functionality. The version with the AXI interface has only one address – the base address, which is used to send the data to.
Sending data to the AD5065 IP
In this code it can be seen that there is a offset of 66060288. This value equals to 11111100000000000000000000, which is the binary equivalent of the command that is writing and updating both DACs. The data is multiplied by 16 because the 4 LSBs of the SPI are not used, hence the value has to be bit shifted to left, which in this case is implemented as multiplication. One last thing - because the 4 MSB and 4 LBs of the SPI are Don’t care bits, even if the user writes something to these bits, the SPI will sent out 0’s.
The source files and 2 test projects built for Zedboard can be found in my Gihub https://github.com/DHMarinov/FPGA/tree/master/Xilinx/Zedboard/AD5065
Where Dual_DAC is a test project that is using the RTL version Dual_DAC_AXI is using the AXI version and ip_repo is the folder that holds the IPs.
This project was used in the TI SWIFT power module test conducted by snidhi. The results can be seen here:
TI SWIFT
Power Module EVM Review: Part 4 Dynamically adjust the output voltage using external DAC
[1] http://zedboard.org/product/zedboard
[2] https://www.xilinx.com/support/documentation/boards_and_kits/ams101/ug886-ams101-eval-card.pdf