I have now finished all ten 4 bit register boards and with them about one third of the soldering (I hope so at least).
So now I am moving on to the construction of the multiplexers but in the meantime I thought I might look into the design of the control logic (a subject I have avoided until now).
My first thought was to use a EEPROM and a 4 bit register along with a clock to drive the register but this did not seem quite right on a transistor computer so I found a alternative;
To keep things small (relatively small) I am limiting my opcode to 4 bits if I want more instructions I can always remove the control board and replace it with the before mentioned EEPROM.
to help remove confusion I will give a explanation of the CPU's timing;
rd means data is taken from the bus and placed in a register and rt means a mux takes data from a register and puts it on a bus.
All registers in the computer are transparent the T (temporary) reg acts to prevent cycling and oscillation.
The T-cycle for T rd and C rd is one half a clock cycle (T rd is high while the clock is high and C rd while the clock is low) and one clock cycle for the rest of the control signals doing this allows for a mux to select a source and place the data in the T reg in one cycle the next cycle is used to rd the data into a destination (the second cycle is only necessary if source equals destination).
The fetch takes six clock ticks;
1: load data at address PC into IR
2: add one to PC result in T
3: PC read
4: load data at address PC into B
5: add one to PC result in T
6: PC read
7: begin to execute instruction
Here is the most up-to-date block diagram of the main data path;
As you may see this is very different from the diagram in the last post but while inspecting it after three months I found many errors and simplifications.
This is the current instruction set but I may very well change this;
- constant to ACC (Is this really necessary?)
- memory to ACC
- ACC to memory
- jump
- jump if zero
- jump if negitive
- jump if carry set
- set carry
- clear carry
- add with carry
- subtract with carry
- and
- or
- xor
- shift right
- halt program (program is resumed when user presses a button)
And now after this brief explanation a diagram of the control logic;
On the AND-plane a given output is high if all inputs for that output are high conversely, on the or plane if one input goes high the all corresponding outputs go high.
The AND gates are to shorten the T rd and C rd signals.
The AND-OR plane will be constructed from diodes and will be approximately five inches wide and six long.
I estimate 100 transistors for the counter, 60 for each decoder, and a dozen or two for the clock and gates this comes to about 220 transistors total bringing the count of the entire computer under 1000.
The counter will be constructed like this;
The clear input is necessary on start up. All FF are edge triggered.
Tim
