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  • Author Author: oldmanraskers
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CPLD Controlled Door Lock - Final Schematic

oldmanraskers

The design has slowed because of work commitments etc. but I have now included an oscillator and the JTAG header - hopefully this is the final design. I will be having a careful look, and if all seems okay I will move onto routing the board. If anyone wants to download the file and comment, please feel free image

Attachments:
imageMain Board.pdf
  • in reply to oldmanraskers

    I can read it now.

     

    A few suggestions:

    I don't like your 24 -> 3.3V regulator - it's far to weedy and will fry. If we assume 100mA it has to get rid of 2W (approx) so you need a decent sized chip  or a switcher. You don't need a switcher for the 1.8V regulator - much better with a linear because even if it has to take 50 mA that's only 75mW.

    A reasonable choice for the linear 3.3V regulator would be:

     

    You don't say the frequency of your oscillator but whatever it is I would put a 47R resistor between it and the CPLD. And I wouldn't put  a capacitor to ground. And I'd use 1uF 0603 caps for chip decoupling everywhere - you've got a mix of 0.01 and 0.1 which is something you often see in app notes but it doesn't work as well as lots of 1uFs.

     

    I would also add some test pins for gnd (more than one of those) and the power supplies and since you have some spare pins on the CPLD connect 8 of them and two grounds to some sort of 10pin connector for debugging. (Then when you are developing the code and it isn't doing what you expect you'll be able to connect a scope or logic analyser to the debug pins and look at interesting signals that you can route out to them.)

     

    MK

  • Ah, I did try to insert the PDF but received a file type forbidden error - but I obviously did something wrong because it is now working image