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  • Author Author: oldmanraskers
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CPLD Controlled Door Lock - Final Schematic

oldmanraskers

The design has slowed because of work commitments etc. but I have now included an oscillator and the JTAG header - hopefully this is the final design. I will be having a careful look, and if all seems okay I will move onto routing the board. If anyone wants to download the file and comment, please feel free image

Attachments:
imageMain Board.pdf
  • in reply to michaelkellett

    I wasn't sure either - I think I will make provision for the cap and leave it out of circuit if not required.

  • in reply to oldmanraskers

    It's badly worded so you can't be sure but I think they mean that it expects to drive a total load of 15pF, so you don't need to add a capacitor.

     

    Tried to post this a while ago (yesterday) but it didn't work - trying again.

     

    MK

  • in reply to michaelkellett

    I'm not really sure what the data sheet means in terms of 15pF - I have attached it if you want to check it out. In terms of the regulator, wow... I am so surprised by the difference in size - I guess the package says it all.

     

    Thanks, MR.

     

    image

  • in reply to oldmanraskers

    Thermal resistance to ambient will tell you how hot the chip will get, I know form experience that a SOT23 size regulator won't get rid of 2W - TI are suggesting about 40degress pwer W for these chips for junction to board and I reckon you'll do very well to manage less than 20 from chip feet to ambient so 2W would give you a max allowed ambient temperature of 30C. It's just easier to use a bigger regulator.

    Putting caps to ground usually interacts with parasitic inductance to make things ring - are you sure the data sheet isn't just telling you that it can drive 15pF ? the series ressitot will often reduce ringing and improve waveforms - but you can always change its value if necessary (and you have a good enough scope to tell the difference.)

     

    I use EasyPC for PCB design - cheap, simple and adequate for most things but running out of steam a bit with >256 pin BGA or when you get to impedance controlled tracks.

     

    MK

  • in reply to michaelkellett

    I'm sorry it took so long to enable visibility image

     

    1.) What should I be looking at in the data sheet to determine if the 24 -> 3.3 regulator will fry?

    2.) The oscillator is 10MHz and the data sheet recommends the 15pF cap, there is no mention of a resistor. I'm willing to take your advice but I'm curious about the design choice?

    3.) Using 1uF caps seems to make sense image

    4.) Ground and power test pins image

    5.) Debug header - you would just run the pins in case you needed to make the CPLD output... anything... like an internal signal etc.?

    6.) What design software do you use for capture and simulation?

     

    Thanks, MR.