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  • Author Author: jc2048
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FPGAs are a Blast!

jc2048

About a week ago I bought myself a USB Programmer for Altera FPGAs and CPLDs. The place I bought

it from also had a small, simple CPLD board based on a Max II part for sale, so I got one of

those too. The pair came to around £16 and arrived the next day via ordinary letter post. It

seemed worth buying the CPLD card simply in order to quickly try out the programmer and convince

myself it worked, though I'm sure I can find some other uses for it.

 

Here's what the CPLD board looks like

 

image

 

I'd previously installed Intel's Quartus software on my laptop to see if it would run ok [the

laptop is still running Windows 8.1]. When I originally did that I had only selected the Cyclone

devices, so as to make the download more manageable, but to use it with this board I now needed

to add the Max devices. Downloading the file was no trouble, but when I tried to install the

devices I couldn't do it. The entry on the Quartus 'Tools' menu for 'Install devices...' didn't

work.

 

image

 

That wasn't very helpful because it didn't tell me the name of the executable to look for. After

a bit of searching, it turned out that the devices can be updated by running the Quartus setup

again. Fortuitously, I'd placed the file alongside the previously downloaded Quartus and Cyclone

devices files, so when the setup was run again it recognised the newly added device file and gave

me the option of updating the install.

 

Next hurdle was the USB. I plugged the programmer in and tried to install the driver. That failed

with an unhelpful error message that didn't give much of a clue as to what had gone wrong. It

turned out that the driver that comes with the current Lite version of Quartus that I'd

downloaded isn't signed and my Windows 8.1 rejects it [but with a vague 'there was an error'

message]. The simple solution, apparently, is to use an older version of the driver [the one that

did install is from 2009 and signed by Altera]. That worked and allows the programmer software to

see the USB programming cable.

 

I've not used Altera tools before, but it's very similar in style to other FPGA integrated design

environments that I've used [the old Xilinx Webpack ISE and Lattice's Diamond], so it wasn't too

hard to write a quick bit of VHDL to test the programmer. This code divides the board's 50MHz

clock by 50 million and then uses the resulting 1Hz-rate enable signal to enable counts of a 4-

bit binary counter.

 

image

 

After I'd corrected the syntax errors, that programmed the board fine

 

image

 

It almost worked. After a bit of head scratching, I realised I'd selected the wrong pin for the

clock input when I was doing the pin assignment.

 

Here are the waveforms displayed on my oscilloscope.

 

image

 

The reason for having it so slow is that originally I was going to light up some LEDs, but in the

end merely settled for showing the waveforms.

  • in reply to jc2048

      wrote:

    The honest answer is that I don't know.

    The reason why I was asking, is because I read the paper, but had a hard time finding real world examples that used the approach.

    When I saw your code, I thought I recognised that pattern ...

  • in reply to jc2048

    I've tried this out on the Xilinx Zynq. Works.

    image

    I've used the ARM to generate the clock, 100 MHz in my case.

    image

     

    image

     

    library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity divider is
    Port ( clk_o : in STD_LOGIC;
           io_1 : out STD_LOGIC;
           io_2 : out STD_LOGIC;
           io_3 : out STD_LOGIC;
           io_4 : out STD_LOGIC);
end divider;


architecture Behavioral of divider is
  signal long_counter: unsigned(25 downto 0);
  signal led_counter_en: std_logic;
  signal led_counter: unsigned(3 downto 0);


begin
  clocked_stuff: process (clk_o)
  begin
    if (rising_edge(clk_o)) then
      if (long_counter = b"00000000000000000000000000") then
        long_counter <= b"10111110101111000001111111";
        led_counter_en <= '1';
      else
        long_counter <= long_counter - 1;
        led_counter_en <= '0';
      end if;
      
      if (led_counter_en = '1') then
        led_counter <= led_counter + 1;
      end if;
    end if;        
   end process clocked_stuff; 
   
   output_connections: process (led_counter)
   begin
     io_1 <= led_counter(0);
     io_2 <= led_counter(1);
     io_3 <= led_counter(2);
     io_4 <= led_counter(3);
   end process output_connections;

end Behavioral;

  • in reply to Jan Cumps

    The honest answer is that I don't know.

     

    I taught myself to use VHDL a long time back (from Scahill's book in the mid 1990s) whilst working in a small company and just having to get designs done and delivered. I wasn't very systematic about it and my coding style is probably appalling.

     

    It's certainly nothing as clever as the paper you link to. (Thanks for the link - I've downloaded it and I'll read it tomorrow and see if I understand it. It looks interesting.)

     

    It might come from things like controlling bidirectional data lines with output enable signals, or something like that.

     

    This is the reason that I don't want to go anywhere near anything that appears like straight tutorials or instruction. I may be able to give a flavour of what it is to do basic engineering, but I'm not going to be of help to anyone who has exams to pass.

  • John, why do you put the assignment of io_1 to 4 in a process?

    I've seen the two-process design method method before. Is that the pattern you are using?