Getting up and running with Arm Design Start, Generating the SW

19 Dec 2018

In my last blog we examined how we could get the Arm Design Start Cortex M3 up and running on out Arty A7-35T board using the example SW application provided. In this blog we are going to look at how we can create our own application software.

To do this we are going to use the following tools

Xilinx Vivado
Xilinx SDK
Arm KEIL
Terminal program such as PuTTY

For this example we will look at how we can build the M3 example on the Arty A7, although the process for a M1 is also the same.

The program for both the Cortex M3 and M1 is stored within the FPGA block RAM as such the outcome of this process will be an updated FPGA bit file.

Lets take a walk through how we create this bit file.

Following completion of the build (shown in the previous blog) we will be in a position to export the hardware description file.

We do this by selecting File->Project-> Export->Export Hardware

We need to export the hardware design to the root of the software directory, this is achieved by selecting the directory in the export hardware dialog as shown below. Note we should map the project directory to the V drive. As we will be coming back to Vivado to update the bit file we do not need to include this in our export.

With the design exported, the next step is to use Vivado to open Xilinx SDK. Again we can do this using File->Launch SDK

To correctly build the application, we need to tell SDK where the exported hardware location and the SDK workspace are located, these are not located locally to the project.

Point the Exported location to the location we have just exported the hardware

The workspace can be found in the path below.

With both of these correctly set, clicking OK will result in Xilinx SDK being opened, within this workspace you will see the hardware definition that was just exported

At this stage we should also check the SDK repositories are as expected, this should point to the following directory V:\vivado\Arm_sw_repository. We can check the repository is correct by selecting Xilinx->Repositories

Note the Global Repository

Just like we do for MicroBlaze and Arm A9, A53 and R5 developments, we need to create a Board Support Package. We can do this selecting File->New->Board Support Package

This will open the BSP creation dialog, leave the project name as the automatic name and click finish.

Clicking finish will open a BSP configuration dialog, double check on the standalone tab the stdin and stdout are connected to the AXI Uart Lite.

Clicking OK will now build the BSP, you may see some warning but if done correctly you will see no errors. The next stage is to generate the ELF file which includes this BSP and the Application. However to do so we will not be using Xilinx SDK.

Instead we will be using Arm KEIL however, before we do we need to copy two files into the BSP include directory.

These files are the xpseudo_asm_rvct.c and xpseudo_asm_rvct.h which are located within Arm SW Repository.

These files should be copied in to the BSP include directory

Before we start with the Arm KEIL software development, we need to ensure we have the following paths mapped correctly in our operating system Path

C:\Keil_v5\ARM\ARMCC\bin
C:\Xilinx\Vivado\2018.2\bin

With that completed, we are ready to open up the Arm KEIL software. We can find an Arm KEIL project under the directory software/m(3/1)_for_Arty_a7/Build_Keil double click on the m(3/1)_for_arty_a7.uvprojx and the program will open.

Once Arm KEIL is open, you will be able to see the files in the BSP under the Standalone folder and the main application under the Main folder.

To build the executable select the rebuild option.

This will generate a new elf and hex file, which will be seen under the Build_Keil directory names bram_a7.elf / hex these files are also copied over to our Vivado directory which is where we need to go back to now to generate the FPGA bit file.

Open a windows command terminal in the directory V:\hardware\m3_for_arty_a7\m3_for_arty_a7

You will notice the BRAM files are also under this directory as well

Within the command prompt run the script make_prog_files.bat this will run Vivado and update the contents of the BRAM which contain the Cortex application. This is a much faster process than rebuilding the entire bit file from scratch.

We are now ready to test our application, to do this we need to use Vivado and the hardware manager in Vivado.

Once the hardware manager is open select the Open Target -> Auto Connect option this will connect to the Arty A7

We can then select the bit file we just generated and program the FPGA, ensure you double check the timestamp on the file to ensure it is the latest one.