The series will use high-voltage FETs in half-bridge configuration.
I have a modular test setup. The design is broken up in two parts
Right: uncommitted motherboard without GaN FETs. It is designed in a way that lets you evaluate power transistors in several configurations.
Top left: daughterboard with 2 GaN 600V FETs (LMG3410) in half-bridge configuration. This board plugs into the motherboard.
Test Bed Design
The two modules, when mated, form a half-bridge with input logic, a power stage and output filter.
The power stage is the core of the story. It's intended to be used in a switch-mode setup. So we'll never try to control the signal in a linear way.
At the output of that stage, there's a filter to remove the switching artifacts from the output and deliver a dc signal.
At the input of the power stage, we have isolators.
They take care that the high voltage of the power stage never reaches the driver stage ( a critical component for the high side of the bridge. More on that later).
The control signal generator module has the duty of generating correct and safe signals for the half-bridge.
For a correct operation of a half-bridge, it is key that we never turn on both FETs together.
And we have to give the circuit a little stabilisation time while switching between the two FETs (dead band).
We just have to provide a PWM signal as input.
The input logic takes care that it is spitted in a signal for the high and one for the low FET. It also ensures that the dead band is inserted in that signal..
In our test bed, this is implemented with discrete gates and RC delay generators. We can as well (and I will) replace this by microcontroller generated signals.
And then there are some utility modules to generate a few dc voltages.
In many cases these wouldn't be worth mentioning. But they are BURR-BROWN converters here. As a fanboy, I will have to deep-dive into that.
Motherboard and Daughterboard
All parts that are not FET-dependent are on the motherboard. Only the parts in the circuit that are tied to a specific FET family are on the daughterboard.
image from Texas Instruments LMG3410 Daughter Card product page
The image above of the daughterboard shows the isolator ICs on the right side, the GaN FETs on the top left.
Local decoupling CAPs and passives that are directly tied to the FETs and isolators are scattered around.
On the backside, not shown here, are dc-to-dc converters that generate necessary high-voltage-side-of-the-isolation utility voltages.
image from Texas Instruments LMG34xx GaN System-level Evaluation Mother Board product page
The motherboard has the low-power driver logic, the input and output filtering and left-side-of-the-isolation dc conversion.
The upper middle part of the board (where the BNC sits) is low voltage. Everything outside the via stitching around that area is high voltage.
There are several ways to mod this board and wander away from its default configuration. I'll visit some of them later.
Simplified Schematic of the Power Stage
The full schematic is available in the evaluation kit user guide. I'm jumping one abstraction step up, so that the main building blocks become apparent.
From left to right, you see the isolation between the driver signal generator and the high voltage side.
Then we have the typical half-bridge circuit, with a high and low transistor. The output is a common LC based low-pass filter.
This is not just there for our safety. There are enough user-accessible parts on the high voltage side of board you can lick if you want.
There is a functional requirement for the isolation - in particular for the one on the high side of the bridge.
To open the upper FET's channel - and keep it open while conducting - we have to drive the gate of that upper FET to very high voltages.
In the case wherethe high FET is open, and the lower FET closed, the drain voltage of the upper FET is almost the Vin (yes, 100's of volts).
And we have to push our gate above that potential to keep the FET conducting.
That's why there has to be an isolation level between the signal generator and the gate.
Our generator can only provide 5 V. That's never enough (several orders of magnitiude too low) to keep that high-side FET open.
The isolator takes care that we can lift (bias) the isolated part of the IC up to the necessary potential,
so that the base level of our driver signal comes close enough to the drain potential of the high-side FET to drive - and keep - it conductive when needed.
The low-side isolator isn't needed per se. Our driver signal has enough potential to drive that FET's gate above ground level (that's the potental of the low FET's drain - it's tied to ground).
We still place an isolator in the path to have the same propagation times in our driver signal on the high and low sided.
If there would be an isolator in the high path and none in the low path, the low signals would arrive faster at the low FET's gate than the ones at the high side.
In situations where we switch fast, that makes a difference.
We would have to compensate for that in our signal generator signal - or we'd have to increase the safety margin in the dead band and compromise efficiency.
|Part 1: Several 100 Volts|
|Part 2: Test Setup with LMG3410 Half-Bridge|
|Part 3: Probing the LMG3410 Half-Bridge|