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Legacy Personal Blogs Offloading Microblaze CRC and packet formatting
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  • Author Author: tcmichals
  • Date Created: 30 Aug 2020 12:36 AM Date Created
  • Views 422 views
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Offloading Microblaze CRC and packet formatting

tcmichals
tcmichals
30 Aug 2020

Offloading the MicroBlaze using two AXI stream compoents

The past several blog postings were about connecting MicroBlaze processor to UART via AXI Stream.  One of the requirements is the serial protocol must have a unique ending byte (EOP) to trigger the DMA that the  buffer is complete. The packet format is loosely based on SLIP/PPP  formatting.  To do this operation on the MicroBlaze requires a TX buffer to format the data..  Also, the packet has a CRC, which requires another pass over the packet. So why not offload this to the FPGA?  The picture below is the TX stream.

 

image

 

Two blocks were added:

  1. axis_tx_protocol_crc.v
    1. Appends a 16 bit CRC to the end of the packet stream.  TLAST is used from the DMA connection to mark the last byte, then add the CRC.  and reset the CRC and wait for the next stream.
  2. axis_tx_protocol
    1. Appends start of packet (SOP), adds ESC formatting if needed when TLAST append EOP.

 

Without offloading/acceleration packet rate was 1.7Mbps, with offloading 2.7Mbps.  If RX stream was done it would provide a 30% reduction in time.  But, if this is done, then a AXI switch can be added and AXI Stream PING block can be created and bypass the processor.  The only reason the MicroBlaze processor is in the "middle" is to get this project kicked off and get my quad-copter in the air.  Over the next few months will add the decode stream and PING block, along with DSHOT AXI Stream etc.

 

Also, the goal is to lower the round-trip time.  The RTT is currently .6ms.  The basicProtocol.h was updated, for TX packet processing: (1) o  use the same formatting, (2) DMA-TX, and (3) FIFO-TX.  The DMA-TX adds the header payload into a RX DMA packet. The FIFO-TX posts the data to memory mapped FIFO.  I have the same project running on a CYC1000 (Altera)  using Wishbone and WB to AXIS and RISC-V. The project is not using a RTOS but protothreads for a basic task switcher.  The code is only a 4Kbytes.  I'm working on the Wishbone to AXI Stream, the issue is the FIFO interface between AXI Stream and Wishbone, trying to do this with one clock cycle.

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