Up to now my counter design uses a master-slave SR flip-flop with asynchronous set and reset (separated from the main set and reset).
The flip-flops are wired so that they form a T flip-flop with the clock being the carry in from the last stage and the inverted output being the carry out to the next stage,
works great as counter as long as the asynchronous set and reset are tied to 5V (they are active low) but now if you pull the reset low on one stage (say the third stage) of the counter and the third stages state is one and the second stage is zero nothing happens! The same is true for the set.
This is do to the fact that the last stage is zero and the carry out is one so the third stages clock input is one which interferes with the set and reset, solution?
Using a edge detector is one option or I could use a adder to increment the contents of a register (built with master-slave D flip-flops) and a mux to select between the adder and the data input (for loading in a new value to be incremented) this would use 30 transistors / stage compared with 24 transistors plus a edge detector for the last design.
Using a adder to increment has the added benefit of being synchronous (and I think cleaner).
I have not tested the later design in hardware yet but if it functions I will use for the program counter(unless something better comes up).