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  • Author Author: subham109
  • Date Created: 27 Oct 2021 7:13 AM Date Created
  • Views 761 views
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Up-Down Counter Design using ZedBoard

subham109
subham109
27 Oct 2021

This is my first technical blog which will introduce the readers to the ZedBoard setup for the programmable logic application. It will help first-time users with the setup and develop their first FPGA project.

 

Getting started with Vivado

 

Step 1:  Open VIvado and click on 'Create Project'. A new window pops up.

Step 2: Hit Next. Add your project name and hit next. Select RTL Project and hit next.

Step 3: Click on Boards and select 'ZedBoard Zynq Evaluation and Development Kit'. Hit Next and then finish.

Step 4:  Add design sources to the project 'counter' and 'clock_divider'. Select the language as Verilog.

Step 5: Write the programs respectively and then set the counter as the top module.

Step 6: Open elaborated design and make the pin assignments. It is recommended to use the documentations for pin assignments.

Step 7: Save the constraints file and then run synthesis.

Step 8: After synthesis run implementation and then generate the bitstream.

Step 9: Open Hardware manager and then click on Auto-Connect. Once the board is detected, click on the program device.

Step 10: Download the bitstream into the board and enjoy learning.

 

How to set up the ZedBoard for programmable logic applications?

 

Step 1:Plug the 12V power supply into the barrel jack (J20). Do not turn on the board

Step 2: Shunt the jumpers JP7-JP11 to the ground.

Step 3: Connect the USB cable(JTAG) to micro USB-B(J17).

Step 4: Slide the power switch (SW8) to the ON position. You will see the green LED (LD13) illuminates.

 

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