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Legacy Personal Blogs YAPS Part Three - Design - LTSpice
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Engagement
  • Author Author: Andrew J
  • Date Created: 29 May 2019 4:39 PM Date Created
  • Views 278 views
  • Likes 3 likes
  • Comments 0 comments
  • bench power supply
  • modular_bench_power_supply
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YAPS Part Three - Design - LTSpice

Andrew J
Andrew J
29 May 2019

EDITS: 11/6/19 - fixed broken links

 

LTSpice files are available on Github.  You will need to put the directory ‘Andrews Parts’ in the sym directory for LTSpice library but you can delete it when finished.  It’s just used to hold the .asy file for the LM7805.

 

I had to learn how to use the application which isn’t the most intuitive, especially the Mac OS version, but I found it extremely useful and I’m really pleased with what I achieved. There are three simulation files: one for the Power Stage, one for Power Control and a combined simulation.   I should apologise that the simulation component references don’t perfectly match those in the schematics.  I prefer the combined simulation: click run and it will undertake a calculation frenzy, completing after 20ms; you could halve that if you get bored!  Attach a ground symbol to the On/Off wire at the bottom to see what happens.

 

I know there will be a view about how I’ve done this but bear with me.  With a lack of experience I wanted to get a “second opinion” as I’d already identified one mistake in the original schematic and the provided LTSpice simulation didn’t match the design very well.  Indeed, once I made some changes to that simulation to match the design, e.g. using the same components, I found it didn’t work so my lack of confidence was well placed!!

 

Ok, so that did lead me a little over the top in reconstructing the simulation by including pretty much the whole circuit in what you see.  However, it really helped identify some issues and allowed me to see the affect of choices I was making.  For example, in the MOSFET used by the Switching Regulator which must be a component with a low RDS(on); without the 0.01uF (10000pf) capacitor on the Set pin connection, the output rippled like crazy.  I can also see the affect of turning the potentiometers (i.e. changing the resistor values) as well as the output load.

 

For those without LTSpice, here’s the simulation:

image

 

The output looks pretty stable as I change the voltage and current limits as well as the output load - here’s some pasted images:

 

image

This shows voltage on OUT and current on RLoad.  The voltage control potentiometer is set at 10K and the Current control potentiometer at 5K; load is 10 ohms.  It's pretty stable with a minor amount of ripple on the current, measured at 233.033 uA.

 

image

Here, I've dialled down the Voltage potentiometer to 650Ohms leaving the Current potentiometer at 5K; load is 2Ohms.  Again, the output is pretty stable: there is some ripple - 2.103mV and 1.112mA.

 

image

This shows the result of dialling down the Current potentiometer to 1K, leaving the Voltage potentiometer at 10K and RLoad at 10 Ohms.  Current is measured at 1.067A and Voltage at 10.672V.  Ohms law calculation would put V at 1.067A * 10Ohms = 10.67.  No ripple to measure.

 

As I play around with the potentiometer settings or RLoad settings I get very similar, stable output graphs.  I can't get it to overshoot in simulation.  Dialling down the Current potentiometer limits the current and the voltage follows accordingly based on the value of RLoad.  I'm reasonably confident the design will work.  I'm quite happy to provide some more graphs, just let me know.

 

Next: Part Four - Design - CalculationsYAPS Part two - Design - Schematic

Back: Part Two - Design - Schematic

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