RISC-V is a new instruction set architecture originally designed to support computer architecture research and education at UC Berkeley. RISC-V is now set to become a standard open architecture for industry implementations under the governance of the RISC-V Foundation. This talk will summarise the benefits of RISC-V and open ISAs for the open-source systems-software community. The first section of the talk will focus on the draft RISC-V privileged specification, including the RISC-V vision for cleaner abstraction between hardware, hypervisors, and operating systems. The talk will also discuss my experience bringing up RISC-V emulation support in QEMU, including adding architectural support, experimental devices, and fuzz testing against Spike, the “golden reference” RISC-V simulator. The talk will conclude by outlining opportunities to contribute to RISC-V ISA support in QEMU.
Sagar Karandikar Graduate Student Researcher, UC Berkeley Sagar Karandikar is a first-year graduate student researcher focusing in computer architecture in the Electrical Engineering and Computer Sciences department at UC Berkeley. His research focuses on hardware and software design of next-generation datacenters. He has also been involved in the RISC-V project, contributing to the development of infrastructure surrounding the open RISC-V Instruction Set Architecture.
From https://wiki.qemu.org/Documentation/Platforms/RISCV . Please read if you have time...
