Cypress Semiconductor PSOC 4,

The Engineers Magic Wand!

Yes I am analyzing architectures again.

When I first saw the 100 projects in 100 days for the PSOC 4 Pioneer Development Kit, I did not have a lot of enthusiasm, mostly because I had not looked into the device.

Well after reading through some of the documentation I can now opine.  In a word “WOW!”

If you thought the PSOC is just another Micro Controller Unit (MCU) you would be wrong, its much-much more.

Lets look at the basic features.

Features

32-bit MCU Sub-system

48 MHz ARM Cortex-M0 CPU with single cycle multiply

Up to 32 kB of flash with Read Accelerator

Up to 4 kB of SRAM

So off the start, you get a solid 32-bit MCU running at 48 Mhz.  Not bad at all for an MCU.

Programmable Analog

Two op amps with reconfigurable high-drive external and high-bandwidth internal drive and Comparator modes and ADC input buffering capability

12-bit 1-Msps SAR ADC with differential and single-ended modes and Channel Sequencer with signal averaging

Two current DACs (IDACs) for general-purpose or capacitive sensing applications on any pin

Two low-power comparators that operate in Deep Sleep

You read it correctly, PROGRAMMABLE ANALOG!  Think about the custom signal control devices you can build and control from within the software.  It that’s not magic, it comes pretty close.

Programmable Digital

Four programmable logic blocks, each with 8 Macrocells and data path (called universal digital blocks, UDBs)

Cypress provided peripheral component library, user-defined state machines, and Verilog input

That’s right, you can build up your own logic devices with the PSOC, within some limitations.  Even better, you can build up command, data and status ports for software control.

If you wanted to take a step into Programmable Logic Devices (PLD) or Application Specific Integrated Circuits (ASIC), you now have an incredibly integrated way to do so.

Low Power 1.71 to 5.5 V operation

20 nA Stop Mode with GPIO pin wakeup

Hibernate and Deep Sleep modes allow wakeup-time versus power trade-offs

PSOC gives you a cool way to interface between legacy, CMOS and current SMD technology, all in one package.  The obsolete component market alone will love this setup.  For a hobbyist or prototype developer, your life just improved immeasurably.

Capacitive Sensing

Cypress Capacitive Sigma-Delta (CSD) provides best-in-class SNR (>5:1) and water tolerance

Cypress supplied software component makes capacitive sensing design easy

Automatic hardware tuning (SmartSense)

Cypress is THE leader in capacitive sensing.  The PSOC provides you with the ability to set up every I/O pin to support capacitive inputs.  You may never have to touch a button again.

Segment LCD Drive

LCD drive supported on all pins (common or segment)

Operates in Deep Sleep mode with 4 bits per pin memory

The PSOC lets you add LCD devices at will.  You can have all kinds of dedicated information outputs for specific functions, especially the new ones you create.

Serial Communication

Two independent run-time reconfigurable Serial Communication Blocks (SCBs) with re-configurable I2C, SPI, or UART functionality

Again, the PSOC has anticipated the legacy device market with the tools you need to access all of the current sensor technology and communication media.

Timing and Pulse-Width Modulation

Four 16-bit Timer/Counter Pulse-Width Modulator (TCPWM) blocks

Center-aligned, Edge, and Pseudo-random modes

Comparator-based triggering of Kill signals for motor drive and other high reliability digital logic applications

The PSOC provides a good range of timer and counter circuits.  More importantly, you can use them to drive the timing on your “special” circuits built with the PLD and PAD blocks.  You have the power to explore your mind in ways you never dreamed.

Up to 36 Programmable GPIO

44-pin TQFP, 40-pin QFN, and 28-pin SSOP packages.

Any GPIO Pin can be Capsense, LCD, Analog, or Digital

Drive modes, strengths, and slew rates are programmable

The programmable I/O is much more extended that those you see for standard MCU devices.  Each PSOC pin can do so much more than the other devices.

PSoC Creator Design Environment

Integrated Development Environment provides schematic design entry and build (with analog and digital automatic routing)

Applications Programming Interface (API Component) for all fixed-function and programmable peripherals

I have not had time to use this software yet, but from the descriptions and demo videos, it appears to be fully capable of supporting all of the additional power the PSOC provides.  Cypress has integrated the hardware and software development into a single package and provides the developer with full control of the pieces to invent a wealth of custom devices.

Programmable Digital

Universal Digital Blocks (UDBs) and Port Interfaces

The PSoC 4200 has four UDBs; the UDB array also provides a switched Digital System Interconnect (DSI) fabric that allows signals from peripherals and ports to be routed to and through the

UDBs for communication and control.

UDBs can be clocked from a clock divider block, from a port interface (required for peripherals such as SPI), and from the DSI network directly or after synchronization.

A port interface is defined, which acts as a register that can be clocked with the same source as the PLDs inside the UDB array.

This allows faster operation because the inputs and outputs can be registered at the port interface close to the I/O pins and at the edge of the array. The port interface registers can be clocked by one of the I/Os from the same port. This allows interfaces such as SPI to operate at higher clock speeds by eliminating the delay for the port input to be routed over DSI and used to register other inputs

The UDBs can generate interrupts (one UDB at a time) to the interrupt controller. The UDBs retain the ability to connect to any pin on the chip through the DSI.

The PLD area is one in which I plan to spend a lot of my rare free time to learn.  I am fascinated by the whole concept of defining logic operations, integrating them into the software and being able to create your own pin arrangement to implement complex logic functions.  The sky is no longer the limit of creation.

GPIO

The PSoC 4200 has 36 GPIOs. The GPIO block implements the following:

Eight drive strength modes:

❐ Analog input mode (input and output buffers disabled)

❐ Input only

❐ Weak pull-up with strong pull-down

❐ Strong pull-up with weak pull-down

❐ Open drain with strong pull-down

❐ Open drain with strong pull-up

❐ Strong pull-up with strong pull-down

❐ Weak pull-up with weak pull-down

Input threshold select (CMOS or LVTTL).

Individual control of input and output buffer enabling/disabling in addition to the drive strength modes.

Hold mode for latching previous state (used for retaining I/O state in Deep Sleep mode and Hibernate modes).

Selectable slew rates for dV/dt related noise control to improve EMI.

Every I/O pin can generate an interrupt if so enabled and each I/O port has an interrupt request (IRQ) and interrupt service routine (ISR) vector associated with it (5 for PSoC 4200 since it has 4.5 ports).

The I/O pins are super flexible.  You have the power to set them up as you need.  Oh, did I mention that the PSOC also supports grouping of pins into a user-defined port!  As I said earlier, this feature is invaluable for interfacing to legacy devices.

Analog Blocks

12-bit SAR ADC

The 12-bit 1 MSample/second SAR ADC can operate at a maximum clock rate of 18 MHz and requires a minimum of 18 clocks at that frequency to do a 12-bit conversion.

The block functionality is augmented for the user by adding a reference buffer to it (trimmable to ±1%) and by providing the choice (for the PSoC 4200 case) of three internal voltage references; VDD, VDD/2, and VREF (nominally 1.024 V) as well as an external reference through a GPIO pin.

The Sample-and-Hold (S/H) aperture is programmable allowing the gain bandwidth requirements of the amplifier driving the SAR inputs, which determine its settling time, to be relaxed if required.

System performance will be 65 dB for true 12-bit precision providing appropriate references are used and system noise levels permit.

To improve performance in noisy conditions, it is possible to provide an external bypass (through a fixed pin location) for the internal reference amplifier.

The SAR is connected to a fixed set of pins through an 8-input sequencer. The sequencer cycles through selected channels autonomously (sequencer scan) and does so with zero switching overhead (that is, aggregate sampling bandwidth is equal to 1 Msps whether it is for a single channel or distributed over several channels). The sequencer switching is effected through a state machine or through firmware driven switching.

A feature provided by the sequencer is buffering of each channel to reduce CPU interrupt service requirements. To accommodate signals with varying source impedance and frequency, it is possible to have different sample times programmable for each channel.

Also, signal range specification through a pair of range registers (low and high range values) is implemented with a corresponding out-of-range interrupt if the digitized value exceeds the programmed range; this allows fast detection of out-of-range values without the necessity of having to wait for a sequencer scan to be completed and the CPU to read the values and check for out-of-range values in software.

The SAR is able to digitize the output of the on-board temperature sensor for calibration and other temperature-dependent functions. The SAR is not available in Deep Sleep and Hibernate modes as it requires a high-speed clock (up to 18 MHz).

The SAR operating range is 1.71 to 5.5 V.

Two Op Amps (CTBm Block) The PSoC 4200 has two op amps with Comparator modes which allow most common analog functions to be performed on-chip eliminating external components; PGAs, Voltage Buffers, Filters, Trans-Impedance Amplifiers, and other functions can be realized with external passives saving power, cost, and space. The on-chip op amps are designed with enough bandwidth to drive the Sample-and-Hold circuit of the ADC without requiring external buffering.

Temperature Sensor

The PSoC 4200 has one on-chip temperature sensor This consists of a diode, which is biased by a current source that can be disabled to save power. The temperature sensor is connected to the ADC, which digitizes the reading and produces a temperature value using Cypress supplied software that includes calibration and linearization.

Low-power Comparators

The PSoC 4200 has a pair of low-power comparators, which can also operate in the Deep Sleep and Hibernate modes. This allows the analog system blocks to be disabled while retaining the ability to monitor external voltage levels during low-power modes. The comparator outputs are normally synchronized to avoid meta-stability unless operating in an asynchronous power mode (Hibernate) where the system wake-up circuit is activated by a comparator switch event.

Those of you who speak Analog will salivate over these programmable analog features.  My mind is already racing with potential applications.

CONCLUSION

To summarize, you need to learn how to exploit the new PSOC devices hitting the market today.  They are the future! 

An MCU’s have enabled a basic level of “programmable” hardware for decades, but it is now time to move forward with a cleaner implementation.

I can honestly say that I am really excited about this new technology.  The PSOC bridges the old way of building special hardware and integrating it into the software.  You get both capabilities in one package, hence my tag of “ The Engineers Magic Wand.”

Trust me, you want to learn this technology as fast as you can.  The current PSOC devices are just the beginning.  Your options for hardware/software solutions just leaped to a new dimension.  The future is going to be a much more interesting place, than I thought it would be yesterday.

DAB