256 x 12 RAM

found a listing  instructions http://www.intel.com/Assets/PDF/DataSheet/4004_datasheet.pdf

Clem

found a listing  instructions http://www.intel.com/Assets/PDF/DataSheet/4004_datasheet.pdf

Clem

I am using 15 instructions.  And the ALU can add and subtract.

The instruction decoder and control logic are separated from the rest of the computer and do not share the memory or data bus.

Are you using an Arduino? Or basic Logic from something like an FPGA?

C

I am only using basic logic,counters,adders etc. And memory.

timswift wrote:

 

I am only using basic logic,counters,adders etc. And memory.

I would suggest looking into an FPGA as a cheap and easy way (once you've come up the learning curve ) to implement logic and memory.  A simple CPU is well suited to the Lattice iCE40 which is the only FPGA I know of that has open-source tools (IceStorm).  There's a really nice low-cost development board (Lattice iCEstick) that unfortunately seems to be out of stock everywhere.  There's a nice educational development board (Nandland Go Board) that completed its Kickstarter funding a month ago and is now in production.  The Nandland web site has good tutorial material for new FPGA users.

I don't know why iCEstick seems to be out of stock so much.  I suspect Lattice loses money on each one sold, and they're being snapped up by hobbyists who use them for one-of-a-kind projects and learning about FPGAs and don't go on to buy iCE40 chips in 100K quantities for commercial products.

You can get started with FPGAs at no cost by simulating your CPU design and waiting to buy an actual FPGA board until your CPU design works.

Thanks for all the good feed back.

I am still working on the design but I would like to build it in simpler pieces then assemble it.

The control logic is the most difficult part so far.

Tim

timswift wrote:

 

The control logic is the most difficult part so far.

Control logic does not need to be difficult.  Most computer design books I've seen don't cover it well, so people get the false impression that it's difficult and mysterious.

The important thing is to have an instruction set that allows you to have a simple data path that's easy to control.  Basically, a computer has a data path that performs all the arithmetic and register transfers and a control unit that tells the data path what to do each clock cycle.  The data path has control points (CPs) that specify what each element of the data path should do.  For example, an ALU has an operation CP to tell it which operation to do and each multiplexer has a mux CP to select one of the mux inputs.

Glen Langdon's Computer Design (1982) has a nice analogy: the data path is like a piano and the keys are the control points.  The human playing the piano is the control unit that activates those control points.

If your instruction set allows a simple data path with a relatively small number of CPs your life will be much easier.  For example, a classic RISC implementation usually allows fields of instructions to map directly to control points.  The register fields connect directly to the CPs that select registers from register files and the opcode field can connect directly to the ALU's operation CP.  If the instruction format allows an immediate operand the bit that selects immediate mode drives a mux CP that selects a register value or the immediate field from the instruction register.

RISC instruction sets usually have simple controllers if not pipelined.  If you do add pipelining, it gets more complex but nowhere as bad as it would be if you try to pipeline a CISC.

If you're not designing a RISC, I suggest looking into Hardware Flowcharts also known as Algorithmic State Machines.  ASMs basically combine finite-state machines with register transfers and are a clean way of looking at and designing control logic.

I have finished the control logic's ruff design. I also changed the commands their are only 12 now (the ALU functions are on the same command).  And the ALU has the highest chip count so far but the design is

relatively strait-forwards.   

Tim