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Linux Kernel Idea

Former Member

Hi,

I have an idea for a modification of the xilinx linux kernel and as i have little development experience i am wondering if anybody can see impending issues with it.

So ... here goes.

I am relatively new to the zedboard but when i was attending a zynq training day i discovered that the driver for loading bitstreams in the linux kernel can load partial areas. This implies that it could be used very dynamically but i havent actually tested this yet.

My idea is to modify the linux loader (and possibly elf format) so that bitstreams can be referenced as a shared library. Also this would allow (with sufficient knowledge of the bitstream) dynamic placement by the linux kernel. Ideally the loader could be modified only slightly, so that there would still be compatibility with non bitstream inclusive files. Additionally programs could be switched between each other by the scheduler based on hardware interrupts etc

I can see quite a few difficult hurdles in the creation of this but only one big glaring issue:
the bitstream format - the EULA from xilinx says: Licensee is not licensed to, and agrees not to: (i) decompile, translate, reverse-engineer, disassemble, or otherwise reduce to human readable form the Software or the data files generated by the Software
... So to achieve this would be in breech of this licence agreement ...

There are quite a few software difficulties but i see no reason why it cannot be done. I think it would be useful/fast to dynamically switch and place any fpga designs.

I haven't done alot of kernel hacking though, so i am wondering if there is anything big/obvious that i am missing

thanks,
Stephen

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  • 0

    Stephen,

    You do not have to re-invent the wheel.  Xilinx has supported the partial configuration flow for our FPGA devices since ISE 12.2 with PlanAhead.

    You do not have to reverse engineer anything, as the flow will create partitions of partial bitstreams, which you may then load into the part directly through the linux interface that causes the configuration interface to look like a device.

    Austin

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  • 0

    Stephen,

    You do not have to re-invent the wheel.  Xilinx has supported the partial configuration flow for our FPGA devices since ISE 12.2 with PlanAhead.

    You do not have to reverse engineer anything, as the flow will create partitions of partial bitstreams, which you may then load into the part directly through the linux interface that causes the configuration interface to look like a device.

    Austin

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  • 0 in reply to Former Member

    Hi Austin,

    Yes, that was what i discovered at the training day. My idea is more integrating this into the operating system. I havent checked but wouldn't the partial bitstreams still be locked to particular areas of the PL?

    I am wondering if i could do this dynamically assuming there were no specific placement requirements such as being attached to an LED. For example, say you had an adder, subtracter, multiplier and divisor. Say there were 15 different C programs, each using a different combination of the above. The kernel could load and switch between them, allowing access to the FPGA from the C Program. My idea isn't to reinvent the partial configuration flow its using it inside the kernel in a library style.

  • 0 in reply to Former Member

    " I havent checked but wouldn't the partial bitstreams still be locked to particular areas of the PL? " Yes they are, because that is how the FPGA configuration process works.
    Configuration process is equivalent of railway turnouts for railway tracks (it is a bit simplified example). In this process you do not chage the location of tracks, nor the stations, but you can change from where to where the train (or FPGA signals) can travel.
    So your partial configuration file is made to configure a particular mode and a particular part of the FPGA chip. It cannot be used for any arbitary part of the FPGA chip.
    Also take note that the reconfiguration process does consume some signicant amount of time.