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Vivado HLS how to interact with Zedboard

jmales

Hello guys,

I was given a task which is to implement a C algorithm (somewhat complex) in an FPGA.

Since I knew nothing about VHDL/Verilog I started looking into Vivado HLS to convert C into VDHL "automatically". After many many tutorial hours, I'm now capable of generating a funcionable and optimized RTL from C code.

Now, I was given a Zedboard, I've been doing some tutorials and this seems like a great hardware. However I have a question related to my task: how am I going to put the Vivado HLS code into the Zedboad FPGA if the only thing I have is the RTL (VDHL files) from Vivado HLS and I know nearly nothing about IP generation in Vivado? Is there any software that converts my VDHL into a bitstream, generates the ports and connections automatically and let's you easily program your FPGA in the Zedboard?

Thank you for the help

  • 0

    Congratulations on learning the Xilinx HLS toolflow!  ZedBoard is a great board to target with your new expertise.

    I see 2 options for your next step - getting the code running on ZedBoard.

    1) In order to use the HDL code to program Zynq on ZedBoard, you'll need to learn a little bit about the Xilinx Vivado tools in order to create a project, compile your HDL code, and program a bitstream into the device on ZedBoard.  The Training and Videos section of this site will help you tremendously.  You can also find Vivado Tutorials on the Xilinx website.  That's the manual method.

    2) The second option is a compelling workflow from MathWorks using their Zynq Support Package.  Their workflow allows you to start a design in Simulink, incorporate existing HDL and C code, and use a push-button flow to automatically generate executable code and run it on the ZedBoard target.  I'd suggest starting with the videos/info on the following page:

    http://www.mathworks.com/programs/xilinx-zynq-design-with-simulink.html

    Good luck!
    -Matt

  • 0 in reply to mbrown

    Thank you for the answer.

    I think I'm going to use the 1st step, it sounds more natural to keep it all within the Xilinx programs.


    So, just one question to clarify. After generating the HDL code from C with Vivado HLS, i need to generate the bitstream and IP in Vivado and then use SDK to send that bitstream to the Zedboard? That seems like an awful lot of work just to program an algorithm into an FPGA...