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Lab 08 - Non Volatile Configuration

Former Member

Hello everyone.

In Lab 8 of ZedBoard tutorials, I got an error of an undeclared variable.
It happens when I create a First Stage Bootloader Project (FSBL) from Xilinx SDK Templates, for my ZedBoard.

This is what I got:

../src/qspi.c:122:6: error: 'XQSPIPS_LPBK_DLY_ADJ_OFFSET' undeclared (first use in this function)
../src/qspi.c:122:6: note: each undeclared identifier is reported only once for each function it appears in
make: ** [src/qspi.o] Erro 1

Since it's a template, I'm not supposed to change a thing. I don't know what that variable means, so I have no clue on how I can get rid of this. If anyone already got this, I'd appreciate to know how you did it.

*
After this, I've run Lab 07 solution, to make sure I didn't do anything wrong before. And I still got this error.

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  • 0 in reply to Former Member

    I'm using ISE 14.4 in win7 64b. But still, I'm running a template made for this version.

    Cheers.

  • 0 in reply to Former Member

    I think the issue is due to differences between how the hardware and/or software are implemented in the two different tool suites.

     

    I unzipped the lab 7 solution and just opened PlanAhead and followed the lab directions. I was able to duplicate your results. To try to bridge the differences between the tool suites I performed the following steps:

     

    After unzipping the Lab 07 solution (should work the same with your result if you completed the labs to this point) I opened the project in PlanAhead and then double clicked on the 'system_i' (system.xmp) file in the 'Sources' pane to invoke the XPS tool. When XPS opens it should detect that you are using a newer version of the tools and ask if you would like to update the project. Say 'Yes'. Once the update is complete click the 'Clean All Generated Files' option under the XPS 'Project' button on the tool bar. Once this is complete use 'File > Exit' to exit XPS back to PlanAhead.

     

    Now, back in PlanAhead, click "Generate Bitstream' under the 'Program and Debug' under Flow Navigator to generate a bitstream with the new design. Ignore/bypass any warnings. Say 'yes' to opening the implemented design. Then go to 'FIle > Export > Export Hardware for SDK' and make sure to check the 'Include Bitstream' option this time to update the exported hardware.

     

    Open SDK and say 'Yes' if it indicates that it has detected a HW update and wants to sync. Once that is complete build the FSBL as directed in the lab instructions, except that you DO want to generate a new BSP to make sure you are up to date with the new design. The build worked correctly for me at this point.

     

    When you go to Create the Image you may need to browse to tell it where the zynq_fsbl_0.elf is and manipulate the order of the three source files in the list of partitions to match the order shown in the lab instructions (Figure 5). The order is important. You may also need to create the /bif Output folder and adjust the destination to match Figure 5 in the lab instructions.

     

    The new image boots for me at this point.

     

    -Gary