Hello,
I followed the instructions in Chapter 3 in the tutorial
"ZedBoard: Zynq-7000 AP SoC Concepts, Tools, and Techniques
A Hands-On Guide to Effective Embedded System Design
ZedBoard (Vivado 2013.2)"
I'm using Vivado 2014.1 instead of 2013.2.
My design looks similar to the one in Figure 3-3: Completed Port Connections, but I get critical warnings when I try to validate the desing:
e.g.:
CRITICAL WARNING: [BD 41-1348] Reset pin /axi_gpio_0/s_axi_aresetn (associated clock /axi_gpio_0/s_axi_aclk) is connected to asynchronous reset source /processing_system7_0/FCLK_RESET0_N.
This may prevent design from meeting timing. Please add proc_sys_reset module to create a reset, that is synchronous to the associated clock source /processing_system7_0/FCLK_CLK0.
You can find my design here:
https://dl.dropboxusercontent.com/u/15987625/myDesign.jpg
Does anyone have an idea, why it doesn't work for me?
Regards,
Yaro