MIG is used to generate a memory controller in the FPGA programmable logic (PL). The only DDR memory on the ZedBoard is connected to the Processor Section (PS) and is not directly connected to the PL section of the Zynq device so you cannot use MIG in this instance.
Gary, do you have some project with Zedboard plate where've implemented the MicroBlaze? Could you send it to me? My problem is that all the examples I have found do not work.Thank you
Thank you for reply. So the only way to interface DDR is thought PS?
Is this correct for all Zynq devices? or only for Zedboard?
What would actually happen if I create only a 'PL' project with MIG IP on Zedboard, since it's providing this option? Moreover it provides an option to have both PS with DDR3 access and a MIG generation as well. Am I missing something?
