Central Interconnect in Zynq7020

Question

Hey,

I'm using the Zynq evaluation kit and I'm looking for documentation about the build in "Central Interconnect".

I have some time critical functions and I want to use the AXI-Master-Port of the Processing System as well as the MIO peripheral. Both are connected to the central interconnect. As far as I recognized all of this ports interfaces at the central interconnect are somehow time multiplexed. For my evaluation about possible bottlenecks I have to know how are they multiplexed and what are the timings?

Does anyone know where I can find a documentation about the central interconnect regarding the above issue?

Best regards

Andy

Former Member · Accepted Answer

Andy,

From the Zynq-7000 overview document (ref link: http://www.xilinx.com/support/documentation/data_sheets/ds190-Zynq-7000-Overview.pdf) on page 6:

"Traffic through the interconnect can be regulated through the Quality of Service (QoS) block in the interconnect. The QoS feature is used to regulate traffic generated by the CPU, DMA controller, and a combined entity representing the masters in the IOP."

You can ensure bandwidth is guaranteed via the QoS feature of the Central Interconnect.

Referencing UG585 (ref link: http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf) on page 116, section 5.1.1 there is the reference that the Central Interconnect is based on the ARM NIC-301 standard.

Here is the link to the ARM website that describes the ARM NIC-301 standard: http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf

Section 1.3.1 is of particular interest. It references this document: http://infocenter.arm.com/help/topic/com.arm.doc.ddi0397f/DDI0397F_amba_network_interconnect_nic301_r2p0_trm.pdf

A good deal of reading, but I believe all the information you need is there. The Central Interconnect is designed by ARM, not Xilinx.

Hope that helps you get started.