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FSM dont run

zanabonir

Dear Forum

I write vhdl code for a very simple State Machine,with a Reset Buttom. I simulate in Vivado with a testbench, and all is working...the machine move every CLK.

So i tried on zedboard in this way:

* I create  a IP and add the FSM code (Vivado create the default 4 register AXI ..) .

* I connect to the Zynq PS + reset system as always

*Mapped the IP  using the xfc file, syntesis,implement and bitstream correct

Problem is that, when sdk program the fpga, the machine dont run..only the reset button work.

Seems clk is not connect.  The CLK for IP is ----S00_AXI_ACLK---- used by default in the IP .

Can I use this CLK ? What can be the mistake.

Thanks very much

Roberto

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  • 0

    Hello Roberto,

    Yes you can use this clock, so long as the jitter that it generates meets the timing needs of your system. ZYNQ has multiple clock trees and levels, here is a brief introduction to Clocks from Best to Worse.

    ·         Transceiver PLL Clocks

    o   specialized for their task, terrible for general purpose use

    ·         PL PLL Clocks

    o   what I tend to use, they are not as flexible as the MCMM, but I think each have their place for the needs one might have

    ·         PL MCMM Clocks

    o   general purpose clock, I wouldn’t PERSONALLY use these over 50MHz, although they can run pretty high…but my experience is typically with high precision stuff (28.000000MHz was not perceive enough for us in a lot of cases, typically took it out to 9 0’s of accuracy

    ·         PS Clocks

    o   these can be inaccurate

    o   accurate clocks are expensive, and with everything being HARDENED, jitter doesn’t matter as much…so these are not the best clocks in the world, but they certainly suit the needs for a general purpose clock that one can use to keep the PL and PS tied together.

    o   Amazingly enough though, since the AXI interface actually takes care of double buffering signaling, using that clock to drive the PL really doesn’t matter (unlike most busses where you would want to use the same clock)

     

    I have a few questions for you. What is your clock rate, how much logic are you using for the IP, and do you have your constraints setup properly? Please try slowing down your clock to test and make sure that is not the issue. 

    --Josh

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  • 0

    Hello Roberto,

    Yes you can use this clock, so long as the jitter that it generates meets the timing needs of your system. ZYNQ has multiple clock trees and levels, here is a brief introduction to Clocks from Best to Worse.

    ·         Transceiver PLL Clocks

    o   specialized for their task, terrible for general purpose use

    ·         PL PLL Clocks

    o   what I tend to use, they are not as flexible as the MCMM, but I think each have their place for the needs one might have

    ·         PL MCMM Clocks

    o   general purpose clock, I wouldn’t PERSONALLY use these over 50MHz, although they can run pretty high…but my experience is typically with high precision stuff (28.000000MHz was not perceive enough for us in a lot of cases, typically took it out to 9 0’s of accuracy

    ·         PS Clocks

    o   these can be inaccurate

    o   accurate clocks are expensive, and with everything being HARDENED, jitter doesn’t matter as much…so these are not the best clocks in the world, but they certainly suit the needs for a general purpose clock that one can use to keep the PL and PS tied together.

    o   Amazingly enough though, since the AXI interface actually takes care of double buffering signaling, using that clock to drive the PL really doesn’t matter (unlike most busses where you would want to use the same clock)

     

    I have a few questions for you. What is your clock rate, how much logic are you using for the IP, and do you have your constraints setup properly? Please try slowing down your clock to test and make sure that is not the issue. 

    --Josh

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  • 0 in reply to jafoste4

    Thanks for your reply.

    What Im doing is using a precompilated file that Vivado generate when we create a new AXI4 interface (Tools-->create and package IP-->...) and modify this file adding my logic...a very simple 4 state machine (2FFlop) witch out goes in a combinatory logic and then to LED . Thi  just for try the first time to add  new device  in FPGA.

    So i did not modify any constrain file..apart mapping some pin of  my machine to the LED od zedboard ( in the xcf file).., but not more.

    No time constrain i canged because for now I have not the knowledge to do this.

    Clk is 100MHZ as preset for zedboard.

    About clock, thanks for your description...I only use PL PLL because Vivado in the zynq property (dbl click on zynq PS in bd)  show only this clk as out ...I will chk better .

     

    Thanks again

    rob