Dear Forum
I write vhdl code for a very simple State Machine,with a Reset Buttom. I simulate in Vivado with a testbench, and all is working...the machine move every CLK.
So i tried on zedboard in this way:
* I create a IP and add the FSM code (Vivado create the default 4 register AXI ..) .
* I connect to the Zynq PS + reset system as always
*Mapped the IP using the xfc file, syntesis,implement and bitstream correct
Problem is that, when sdk program the fpga, the machine dont run..only the reset button work.
Seems clk is not connect. The CLK for IP is ----S00_AXI_ACLK---- used by default in the IP .
Can I use this CLK ? What can be the mistake.
Thanks very much
Roberto
