How hard to add 3x gigabit Ethernet ?

Is the Ethernet port logic cut and paste and add 3x MAC-PHY?

Does anyone have a feel for the scope of work required to add 3x Ethernet?

Thanks in advance,

-Ed

0 Former Member over 13 years ago

I think you can use IP Block from Xilinx for MAC (Maeby need licence from Xilinx) and create 3x PHY card with FMC connector.

Zynq have 2 MAC blocks. So you need to create 2 MAC controllers in logic area.
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0 Former Member over 13 years ago

Limba is correct that the flow will be to use Xilinx MAC IP within the fabric, with a PHY external, and drivers written to interface with the Linux Kernel to take advantage of the additional MACs.
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0 Former Member over 13 years ago in reply to Former Member

I appreciate it. I am glad it sounds possible.

Thanks again,

-Ed
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0 Former Member over 13 years ago in reply to Former Member

Hi ,
Not sure if the 2 Gigabit Ethernet Peripherals are free (Hard Core) or does Xilinx require you to purchase a Licence for the 2 TEMACs.
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0 Former Member over 13 years ago

One idea is to use external switch IC with RMII/GMII and route this to free hard MAC block.

Note:
I was thinking of NAT. 4 LAN input and one WAN connection
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0 bhfletcher over 13 years ago in reply to Former Member

The two Gb Ethernet MACs interface directly to the ARM processor system and are hard core. No license is required to use them.
Bryan
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0 bhfletcher over 13 years ago

The ZedBoard implements one 10/100/1000 port with an external Marvell PHY and the TE PlanarMAG RJ45. The 2nd internal MAC could be routed through EMIO. You would then need to implement the 3rd MAC in PL.

Although I'm not aware of any existing hardware that does this, you could design an FMC module with the 2x Gb Ethernet PHYs/connectors. EMIO as well as the PL logic MAC could both be interfaced through the LPC-FMC, which has 68 I/Os.

Bryan
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0 Former Member over 12 years ago in reply to bhfletcher

Hi Fletch,

In my design we are trying to copy the zedboard but we need two ethernet for the application with little more changes in the design.
Could you please tell us whether we can use the MDIO/MDC pins common for both PHY or do we need to use EMIO for second ethernet?

Thanks and regards,
ATUL KUMAR SINGH
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