Hi,
i am using vivado 2014.1 and petalinux 2014.2. i need to transfer the data from programmable logic to processor system. can you give the suggestions what are the signals should be enabled for communication and what are the blocks should be routing in vivado 2014.1.
Thanks & Regards,
srinivas Rao
Hi Srinivas,
I have one suggestion that you can apply immediately since we have an online training course which shows an example of how to create a custom IP block in Verilog and attach it to the AXI GP interconnect to allow the processor to read/write to registers. If you take a look at our Developing Zynq
-7000 All Programmable SoC Hardware (Vivado 2013.3) training course on the microzed.org site, there is a Lab 7 hands on activity which demonstrates how to add a piece of HDL code to control a PWM output into a custom IP block so that it can be connected to the Zynq Processing System memory space:
http://microzed.org/support/trainings-and-videos
The online course requires registration but is available free of charge. You could use the concepts covered in this hands on lab with your ZedBoard and complete the acitivity using Vivado 2013.3 tools. Vivado 2014.1 should work similarly but you may find that some of the screenshots in the lab documents differ from the windows you encounter in Vivado 2014.1 tools.
Regards,
-Kevin
