Hi~
I would like to theoretically know how TMDS33 is converted to LVDS from the link below .
http://zedboard.org/sites/default/files/documentations/AES-ZED-LCD-INT-SCH-V1_0.pdf
Thanks for reading.
Best Regards,
Asher
Hi~
I would like to theoretically know how TMDS33 is converted to LVDS from the link below .
http://zedboard.org/sites/default/files/documentations/AES-ZED-LCD-INT-SCH-V1_0.pdf
Thanks for reading.
Best Regards,
Asher
Hi Asher,
It is a good inquiry since looking at the schematic, the design principle at work may not be obvious. I attached some images to this post which do not always render properly in every browser. I use Firefox with this site and this seems to work fairly well.
That ALI3 Pmod Interposer Board provides signal connections (LVDS & control signals) to the LCD display panels used in our display kits.
On ZedBoard, there are two I/O Expansion PMOD Headers (JC1 & JD1) connected to PL of ZC7020 device with differential trace routing. These signals are connected to ZC7020 Bank13 with 3.3V Vcco. The High Range (HR) I/O bank does not support LVDS I/O standard with 3.3V supply (on ZedBoard this bank is fixed at 3.3V) and allowed supply voltages for LVDS are only 2.5V/1.8V. Thus, ZedBoard alone is not able to directly support the LVDS33 I/O standard required by the LCD display panel.
To resolve the issue, the differential I/O standards TMDS which supports 3.3V Vcco in the HR bank is employed within the ZC7020 device. Thus, modification of the signaling from ZedBoard is required to convert from TMDS to LVDS33 for compatible signaling standards.
The TMDS signaling standard is widely used in DVI and HDMI video interface. The conceptual schematic of one TMDS differential pair is illustrated below. Using current drive to develop the low voltage differential signal at the receiver side of the DC coupled transmission line. The link reference voltage AVcc sets the high voltage level on the differential signal, while the low voltage level is determine by the current source of the transmitter and the termination resistance at the receiver side. The termination resistance (RT) and the characteristic impedance of the trace/cable (Z0) must be matched. The normal high level voltage is AVcc and the normal low level voltage of the signal is (AVcc – Vswing). According the specification AVcc is 3.3V, RT is 50 Ohms and Vswing is between 400mV to 600mV on transmitter side.
The signal strength is close to LVDS signal except for the DC signal level. In TMDS, the differential signal swing below the supply voltage, but in LVDS, the differential signal swing across the reference voltage, also call common mode voltage Vcm = (Vp + Vn)/2 = 1.2V. About the signal swing magnitude on TMDS (in many cases) is also suitable for LVDS. From the above signaling mechanism, the high level is determined by AVcc, thru we can change new supply voltage on AVcc that match the LVDS signal level. i.e. 1.2V + Vswing(max)/2 ~ 1.5V.
Please note that we adopt TMDS IO Standard on FPGA for differential output and signal level conversion. The data transmitted on those differential pairs are scrambled LVDS data mentioned in the LCD Module datasheet.
After implementing the signal modification of ZedBoard output, a measurement on LVDS CLK signal as shown below to verify the signal level translated from the TMDS output. The measuring point is at the LVDS 100 Ohm termination resistor on the LCD module.
Probe Channel 1 (Yellow): CLK_P
Probe Channel 2 (Blue): CLK_N
The following chart shows the LCD input requirement:
From the measurement above, the DC signal peak value is 1.5V which is < 2.4V.
The common mode voltage is 1.2V and the differential input minimum on high signal is +250mV and -170mV for low signal input, which meets the LCD display panel requirements.
Best Regards,
-Kevin
