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PlanAHead and VHDL-Verilog design

Former Member

A simple question

what is the best way to design and debugg some vhd file when you are creating and working on a project from planAhead - xps?

i got used to creating my stuff with these two - they are really great once we have gone through the tutorial. And i start creating more complex projects which involve writing my vhd code.
by now i used to write it by hand, mostly modifying "user_logic.vhd" but now i would like to create different level of implemantations and i need syntax debugging, and to me, it is not obvious how we are supposed to do so.

At now the only solution i came up with was to create an ise project with my vhd files including user_logic, doing my work, and then copy the result back into my planAhead project.

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    thanks for your answer.

    general process using planAhead links us to generate a .bit and different kind of folders, mainly IPCORE where we are supposed to code our own vhdl.

    my personnal vhdl is programmed inside ISE.
    if i generate a .bit inside ISE that is not relevant to me, in the sense that planAhead generates the .bit with all the hardware specifications related to CPU PS7. that .bit wouldnt be the one we upload to the fpga right?

    samely i dont see how you would link a proper ise project including one or many .vhd constrained by one .ucf to a planAhead project ready to be deployed on the zedboard (since planAhead allows us to create a .ucf for our application .ucf which is located to a particular place, which is /project/constr/new/my.ucf )

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    thanks for your answer.

    general process using planAhead links us to generate a .bit and different kind of folders, mainly IPCORE where we are supposed to code our own vhdl.

    my personnal vhdl is programmed inside ISE.
    if i generate a .bit inside ISE that is not relevant to me, in the sense that planAhead generates the .bit with all the hardware specifications related to CPU PS7. that .bit wouldnt be the one we upload to the fpga right?

    samely i dont see how you would link a proper ise project including one or many .vhd constrained by one .ucf to a planAhead project ready to be deployed on the zedboard (since planAhead allows us to create a .ucf for our application .ucf which is located to a particular place, which is /project/constr/new/my.ucf )

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