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PlanAHead and VHDL-Verilog design

Former Member

A simple question

what is the best way to design and debugg some vhd file when you are creating and working on a project from planAhead - xps?

i got used to creating my stuff with these two - they are really great once we have gone through the tutorial. And i start creating more complex projects which involve writing my vhd code.
by now i used to write it by hand, mostly modifying "user_logic.vhd" but now i would like to create different level of implemantations and i need syntax debugging, and to me, it is not obvious how we are supposed to do so.

At now the only solution i came up with was to create an ise project with my vhd files including user_logic, doing my work, and then copy the result back into my planAhead project.

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    "my personnal vhdl is programmed inside ISE.
    if i generate a .bit inside ISE that is not relevant to me, in the sense that planAhead generates the .bit with all the hardware specifications related to CPU PS7. that .bit wouldnt be the one we upload to the fpga right?"

    In ISE you will generate the .bit which get implemented on the PL of your zed board and if also get implemented on planahed then again it will also configure the PL portion..It has nothing to do with CPU PS7. CPU PS7 is hard core though it is programmable but not by .bit, in SDK PS7_init.tcl file will program PS7. Make one thing clear that if you upload .bit in ZED then only PL is getting used.

    @ your 2nd qsn, in .ucf, you can put your constraints that could be pin number,area constraints , time constraints, if you have many .vhd then you can create a top module, which can all constraints..In ISE or plan-ahead you can do so.

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    "my personnal vhdl is programmed inside ISE.
    if i generate a .bit inside ISE that is not relevant to me, in the sense that planAhead generates the .bit with all the hardware specifications related to CPU PS7. that .bit wouldnt be the one we upload to the fpga right?"

    In ISE you will generate the .bit which get implemented on the PL of your zed board and if also get implemented on planahed then again it will also configure the PL portion..It has nothing to do with CPU PS7. CPU PS7 is hard core though it is programmable but not by .bit, in SDK PS7_init.tcl file will program PS7. Make one thing clear that if you upload .bit in ZED then only PL is getting used.

    @ your 2nd qsn, in .ucf, you can put your constraints that could be pin number,area constraints , time constraints, if you have many .vhd then you can create a top module, which can all constraints..In ISE or plan-ahead you can do so.

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