What is the speed of the clock used on the board for the FPGA ?Can I decode a 50 MHz serial signal with this ?David.
daviddlc,Per the schematic (http://zedboard.com/misc/files/ZedBoard_RevC.1_Schematic_preliminary.pdf) the clock source into the PL (Programmable Logic) is 100MHZ.What is the signal that you are sampling? Is it asynchronous? Digital? Analog?Also, you can always use internal PLL's to increase the speed of the input clock to much higher.
