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Avnet Boards General Need to Build a Large FIFO on Zedboard
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Need to Build a Large FIFO on Zedboard

Former Member
Former Member over 11 years ago

I am using the Zedboard and I am in the need of a large FIFO to buffer data in the PL to eventually move the data to the PS. Currently I am trying to populate a 32 bit wide with at least 500000 depth FIFO buffer but there isnt enough resources in the Zedboard. I am wondering what other possible solutions I have?

One thought was creating multiple FIFOs with diefferent resources (distirbuted ram, BRAM, and FIFO36 blocks) then route the data as each one gets filled up. It seems however that the FIFO36 and the BRAM options use similar resources so I still have a problem. When I try to run the distributed RAM option with huge depth IP doesnt seem to get generated when I start synthesis.

Another thought was using an expansion board. Are there any FMC or PMOD expansion boards that I could use to expand on the exisiting logic in the Zed board? Or can I use another zedboard or microzed to expand?

Any other ideas that might be useful?

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  • drozwood90
    0 drozwood90 over 11 years ago

    omh11,

    There is four PL DMAC (DMA Controller) in the Zynq.  It also has 4 PS interfaces for 8 concurrent links.

    There are also 8 interrupt lines.  You will have to write some DMAC code to make this work.  It is listed on User Guide 585 (UG585).

    •   AXI Central DMA (CDMA)  
          
      •     Memory-to-memory operations
      •  
    •   AXI DMA  
          
      •     High Bandwidth DMA
      •   
      •     Memory to/from AXI Stream-type  peripherals
      •  
    •   AXI DataMover  
          
      •     FIFO Memory Mapped to Streaming
      •   
      •     Streaming AXI interface alternative to traditional DMA, no Scatter Gather
      •  
    •   AXI Video DMA  
          
      •     Optimized for streaming video application to/from memory
      •  

    For you, you are probably looking at AXI Datamover or AXI Central DMA.  They can be found in the IP chooser in Vivado.  These DO use the High Performance ports.  The AXI GPIO pins are typically used for much slower things such as SPI/I2C/controlling BITS directly in the PL fabric.

    --Dan

     
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  • Former Member
    0 Former Member over 11 years ago in reply to drozwood90

    Dan,

    Ever since your post I've been struggling with the Datamover and could not get it to work. Is there any good examples you can reference me to? especially for S2MM.

    Thanks!

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  • Former Member
    0 Former Member over 11 years ago in reply to drozwood90

    Dan,

    Ever since your post I've been struggling with the Datamover and could not get it to work. Is there any good examples you can reference me to? especially for S2MM.

    Thanks!

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