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External PL clock for Zed Products

Former Member

I understand the Zedboard is capable of receiving an External PL Global clock via the FMC or one of the PMod ports.

Is this the case for both the MicroZed and PicoZed also? If so , could you direct me to the FMC or carrier board pins that are used for this. I would like to verify before making any purchases.

I have seen where the PL clock can be supplied from the PS as a selection of 4 different clock sources but very little documented that I've read on an external clock.

Regards,
Lee.

  • 0
    Zynq PL has two types of clock-capable pins:
     
    1. MRCC
    2. SRCC
     
    SRCC stands for Single Region Clock Capable, and MRCC stands for Multi Region Clock Capable.  For those familiar with previous Xilinx FPGA families, these are similar to the GCLK pins.  For those who are not familiar these pins are used for bring clocks in and out of the FPGA.  These pins are dedicated resources that reduce clock skew and jitter.  If you are clocking something out of the fabric, or reading something in with a reference clock, you want to put the clock on an SRCC or MRCC pin.  Take a look a the clocking guide to find out more about which each of these do.
     
    On MicroZed and PicoZed, the locations of the MRCC and SRCC are as follows:
    MRCC:
     - JX1_LVDS_11_P/N (JX1 42,44)
     - JX1_LVDS_12_P/N (JX1 47,49)
     - JX2_LVDS_11_P/N (JX2 48,50)
     - JX2_LVDS_12_P/N (JX2 53,55)
     - BANK13_LVDS_1_P/N (JX1 88,90)
     - BANK13_LVDS_7_P/N (JX3 73,75) PicoZed Only
     
    SRCC:
     - JX1_LVDS_10_P/N (JX1 41,43)
     - JX1_LVDS_13_P/N (JX1 48,50)
     - JX2_LVDS_10_P/N (JX2 47,49)
     - JX2_LVDS_13_P/N (JX2 54,56)
     - BANK13_LVDS_0_P/N (JX1 87,89)
     - BANK13_LVDS_8_P/N (JX3 74,76) PicoZed Only
     
    Here's where a few of these MRCC/SRCC are accessible on a few of the Avnet Carriers:
    MicroZed FMC Carrier:
     - FMC: 4 MRCC, 3 SRCC
     - Pmod JY: 1 SRCC and 1 MRCC
     - Pmod JA: 1 SRCC
     
    MicroZed IO Carrier:
     - 100 MHz single-ended clock: JX2.48, MRCC
     - Pmod JC: 1 MRCC, 1 SRCC
     - Pmod JY: 1 MRCC, 1 SRCC
     - Pmod JG: 1 MRCC, 1 SRCC
     - XADC header: 1 SRCC
     
    PicoZed FMC Carrier:
     - FMC: 4 MRCC, 3 SRCC
     - PMOD1: 1 SRCC
     
    Bryan
  • 0

    Thank you Brian for your informative and detailed reply. Not only did I receive the information I requested but I also learnt something new in the process. Well done.

    Lee.