Hi everybody,
I am trying different designs of communication between PL and PS. I am already familiar with quite complicated designs using BRAM and DMA.
My question:
Is there a hurdle in general to connect Master AXI Full peripheral (custom one, generates data) -> Axi Interconnect -> S_AXI_HP0 of Zynq and just send data directly to DDR ?
Could I get a little bit of theory why/how (whether it is feasible or not).
I have tried to write some data this way, but PS cannot read the data (it just freezes). I havent debugged it yet, maybe I am writing somewhere to memory, where it is inappropriate. (Or I might misunderstand the design).
