Hello!
I am using a ZedBoard with the System Generator, Matlab/Simulink and Vivado 2014.4. Suddenly when I add another input or output (FMC connector) there is an error creating the bitstream. I cannot see any difference to the inputs or outputs that are working on the model already. I read that there are files for the constraints. Unfortunately I do not have any possibility to edit those files - the workflow advisor creates them.
Why is this error suddenly occurring? How can I enter those constraint files?
ERROR: [Drc 23-20] Rule violation (NSTD-1) Unspecified I/O Standard - 8 out of 1
52 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a use
r assigned specific value. This may cause I/O contention or incompatibility with
the board power or connectivity affecting performance, signal integrity or in e
xtreme cases cause damage to the device or the components to which it is connect
ed. To correct this violation, specify all I/O standards. This design will fail
to generate a bitstream unless all logical ports have a user specified I/O stand
ard value defined. To allow bitstream creation with unspecified I/O standard val
ues (not recommended), use this command: set_property SEVERITY {Warning} [get_dr
c_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_
runs Tcl command), add this command to a .tcl file and add that file as a pre-ho
ok for write_bitstream step for the implementation run. Problem ports: W_L1_pin[
0:0], DIO_MISO1_pin[0:0], DRDY1_pin[0:0], W_H1_pin[0:0], U_H1_pin[0:0], U_L1_pin
[0:0], V_H1_pin[0:0], V_L1_pin[0:0].
ERROR: [Drc 23-20] Rule violation (UCIO-1) Unconstrained Logical Port - 8 out of
152 logical ports have no user assigned specific location constraint (LOC). Thi
s may cause I/O contention or incompatibility with the board power or connectivi
ty affecting performance, signal integrity or in extreme cases cause damage to t
he device or the components to which it is connected. To correct this violation,
specify all pin locations. This design will fail to generate a bitstream unless
all logical ports have a user specified site LOC constraint defined. To allow
bitstream creation with unspecified pin locations (not recommended), use this co
mmand: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When usin
g the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this comman
d to a .tcl file and add that file as a pre-hook for write_bitstream step for th
e implementation run. Problem ports: W_L1_pin[0:0], DIO_MISO1_pin[0:0], DRDY1_p
in[0:0], W_H1_pin[0:0], U_H1_pin[0:0], U_L1_pin[0:0], V_H1_pin[0:0], V_L1_pin[0:
0].
Thanks in advance!
