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QSPI as normal Flash

zanabonir

Dear Forum

Im playing whit the QSPI via baremetal code,using the I/O mode because of  possibility to write ...some not possible with the Linear Mode.

In particular,im using the Quad Mode.

 Before post my code, partially working , maybe is better I understand some parts in datasheet.Question are:

1)Datasheet 12.2.3 IO Mode Transmit Register

What meas the phrase before the table -The user must empty the TxFIFO beetwen consec......-

And i cant understand the table also

2) Why in datasheet 12.3.3,  the point 4 -Enable Controller- is in this position and not before ?

I means, is not normal ,before of all, Enable the controller, Configure it ,and at last enable the CS ..and so start operation?

Thanks for help

Roberto

  • 0

    Hello Roberto,

    Could you provide me a link to the data sheet you are looking at please?

    --Josh

  • 0

    Hi Robiberto,

    1)      FIFOS work as in First in first out.  I think they want you to flush the FIFO so that the empty flag flips on the FIFO.  That flag is probably used to tell later logic that we are DONE, reset your state machine to IDLE and await a new command.  If you read the documentation, it specifically states that each access to the register corresponds to a write to the TxFIFO.  Through stopping and flushing, it is telling the mechanisms that the next data that goes in, will need to be a new command (read/write).  Do not mistake a FIFO for a pipeline.  They can be used that way, but in this case, it is just a way that Xilinx is using to MASK the pin combinations and commands that need to go to the QSPI memory from software.  In SW land, you just issue register accesses.  The QSPI state machine then translates to controlling the memory.  Hence, finish one command before starting another.  Again, this is NOT a pipeline.  It is a register.  1 deep.  The FIFO allows you to DUMP a load of data into 1 register to allow the processor to go about its business.

    2)       There is probably a state machine in there, it needs to be reset to IDLE before you can configure it and run it.  Hence being disabled, you configure, enable, it does magic, then you disable to bring it back to IDLE ready for the next action.  It also needs to be enabled before you try to assert any IO controls to QSPI memory.  If the controller is not ready, you cannot be certain the correct initial state is ready and you could end up confusing the QSPI through providing erroneous or undefined configuration to the memory.

    I would like to state that this is our interpretation of this. I would suggest you contact Xilinx for a more definitive answer.

    --Josh

  • 0 in reply to jafoste4

    Thanks for reply Mr Foster..and for time you spend in it

    If could be intresting I can post the code, that work good in some part, but not in other.

    Else, I can consider solved this post.

     

    Thanks again

    Roberto