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IO Through Pmod Port

Former Member


Is it possible to use one of the individual pins of one of the Pmod ports as a digital output?  I am starting simple with this zedboard and I am thinking of just using a flipflop in the PL and routing it to a Pmod pin.  Can I do that with one of the 64 GPIO available?

  • 0

    You sure can!  Referencing the Zedboard Schematic found here: http://zedboard.org/documentation

    You can see on page 3 are all 5 PMOD connectors.  One of these labeled MIO, and is attached to Bank 500, which is accessable via the PS.  All other four PMOD's are accessable via the PL IO of Zynq-7000.

    If we were to look at the JA1 connector, pin labeled JA1, we can follow it Sheet #9, where in Bank 13 we see it is attached to pin Y11.

    Placing this line into your UCF file:

    NET my_output LOC="Y11";

    will connect any signal on your top module named "my_output" to the output pin.  Here is what the VHDL port statement would look like:

    PORT(
      clk : in std_logic,
      my_input : in std_logic,
      my_output : out std_logic
    );

    Hope that helps!

  • 0 in reply to Former Member

    I want to test the IO frequency of Pmod,I link JA1 to JB1.

    Set JA1 out,JB1 in,and JB1 light LD0.

    But I have something wrong In the below code,could you help me? Thinks!

    module test(
        input GCLK,
    t output [7:0] LD,
    t output JA1,
    t input JB1
    t );
    reg clk;
    reg data = 1'b0;
    reg [7:0] LD_reg;
    reg [3:0] CLK_counter = 0;

    wire JA1;


    assign LD = LD_reg;
    assign JA1 = data;



    always@(posedge GCLK)
    begin
        if(CLK_counter==20/2-1)
    t begin
    t     CLK_counter <= 0;
    tt  clk <= ~clk;
    tend
    telse
    t     CLK_counter <= CLK_counter+4'b1;
    end

    always@(posedge clk)
    begin
    t LD_reg[0] <= JB1;
    t LD_reg[1] <= 0;     
        LD_reg[2] <= 0;
        LD_reg[3] <= 0;
        LD_reg[4] <= 0;
        LD_reg[5] <= 0;
        LD_reg[6] <= 0;
        LD_reg[7] <= 0;
    t data = ~data;
    end
    endmodule

  • 0

    1. Don't use flip-flops to generate a new clock. Clock all the logic from GCLK. Use the CLK_counter as a clock enable to regulate the speed of the JB1 inversion. The Xilinx forums discuss this topic regularly.
    2. In the second 'always' block, use data <= ~data, not data = data. ISE gives an error if = and <= are both used in the same clocked process.
    3. clk is never initialized

    ---
    Joe

  • 0 in reply to Former Member

    Thanks a lot for your reply,it help me a lot.
    In addition,I want to confirm the GCLK,is 100M or 200M?

  • 0 in reply to Former Member

    It is 100M.  I am having trouble reading from the port W12.  Can I just make the verilog statement "assign LED1 = (Net with loc W12) and the LED will light up when I connect 3.3 volts to JB1?